Bang‐bang cycle‐slip detector improves jitter‐tolerance in SONET PLL/DLL CDR

The phase‐locked loop circuit (PLL) cycle‐slips (CS) phenomenon is a problem in two‐level baseband clock and data recovery (CDR) data‐synchronization. A singular example is that of a CDR synchronizer that uses a PLL in cascaded with delay‐lock‐loop (P/DLL) architecture. The CS issue is most evident when testing jitter‐tolerance to sine‐modulated jitter, particularly for sine‐modulated jitter‐frequencies near the PLL bandwidth. Reuse of a bang‐bang frequency‐detector, already on board of reference‐less CDRs, does CS detection and provides for suppression producing a clean demodulation. In the cascaded‐DLL of Rhee's P/DLL [1], this CS‐suppressed PLL‐clock assures proper DLL operation to broadband the jitter‐tolerance recommendation of the synchronous optical network (SONET). Copyright © 2016 John Wiley & Sons, Ltd.     

Fast settling frequency synthesizer with two‐point channel control paths

A frequency synthesizer with low‐power and very short settling time is introduced, which utilizes two‐point channel control paths. While the main‐path is the same as normal channel controls, a digital‐to‐analog converter (DAC) with tunable gain is used for the compensation‐path to form a feed‐forward direct voltage‐controlled oscillator (VCO) control path. When the two paths are ideally matched, the two‐point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor‐loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near‐zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase‐locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is ? 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.     

Phase‐Locked Loop Using Complex‐Coefficient Filters for Grid‐Connected Inverter

Recently, photovoltaic (PV) power systems have attracted considerable attention in attempts to mitigate global warming. In a PV power system, it is necessary to synchronize the grid voltage when a PV inverter is interconnected with a grid. This paper proposes a high‐speed and high‐precision phase‐locked loop (PLL) using complex‐coefficient filters for a single‐phase grid‐connected inverter. The proposed PLL can detect the phase of grid voltage that has superimposed harmonic components for grid fault. Moreover, numerical results show the effectiveness of the proposed method.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

Robust stability analysis and improved design of phase‐locked loops with non‐monotonic nonlinearities: LMI‐based approach

Due to nonlinear nature of several phase detectors, linear approximation method often leads to performance degradation in many phase‐locked loops (PLLs), particularly when the phase errors are sufficiently large. A third or higher order PLL, in spite of the ability to track a wider variety of inputs and having higher operating‐frequency range, requires more design attention in order to ensure stable tracking. In this work, with the nonlinearities inserted into the system's model, suitable criteria that take into account the nonlinearities' non‐monotonicity, sector and slope bounds are employed to establish robust stability conditions. The result is applicable to any PLLs without order and type restrictions. For Type‐1 PLLs, the resulting condition can be used to search for the maximum stable loop gain, which is also linked to the lock‐in range of the system. In the later part of this work, the focus is devoted towards designing PLLs with high lock‐in range, which is performed via mixing the proposed method with H _∞ synthesis. The searches for the parameters in both PLL analysis and design are expressed in terms of convex linear matrix inequalities, which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples and simulations are included with comparisons over conventional methods. Copyright © 2017John Wiley & Sons, Ltd.     

Optimal frequency tracking method for phase‐shift PWM inverter

This paper proposes a new resonant frequency tracking control method for full‐bridge‐type high‐frequency inverters. Whereas the ordinary phase‐locked loop (PLL) based frequency control method uses a current sensor and a voltage sensor, the proposed technique can achieve the same purpose with a single current sensor. In high‐frequency power supply systems using a PLL, it is impossible to perform power control with an inverter. Therefore, an active converter must be used for power control, and the system grows larger. On the other hand, high‐frequency inverters using the proposed control system simultaneously enable power control and achieve the same resonant frequency tracking as a PLL, and thus high‐frequency power supply systems become extremely simple. This paper explains in detail the principle underlying the control method, and presents an example of a circuit to realize it. The theory is backed up by using a prototype high‐frequency power supply system which actually employs the proposed control system, thereby demonstrating its practical utility in industry. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Control of Uninterrupted Switching Using a Virtual Synchronous Generator Between Stand‐Alone and Grid‐Connected Operation of a Distributed Generation System for Houses

The home applications of distributed generations facilities such as photovoltaic and gas engine cogeneration systems are growing and many distributed generations are connected to a grid by a DC/AC inverter. The DC/AC inverter is controlled by a phase‐locked loop (PLL) in order to be synchronized with the power system frequency. However, the control scheme of stand‐alone operation uses voltage control, and the PLL is unnecessary. Therefore, it is hard to realize uninterrupted change between stand‐alone and grid‐connected operation. In this paper, we propose a virtual synchronous generator control scheme in order to use the same control scheme in stand‐alone and grid‐connected operation. We carried out experiments to demonstrate the control characteristics.     

Analysis and effective controller design for the cascaded H‐bridge multilevel APF with adaptive signal processing algorithms

The cascaded H‐bridge (CHB) multilevel inverter is being recognized as the most suitable topology for high‐power medium‐voltage power quality conditioning applications. This paper presents mathematical modeling and effective controller design methodology for the CHB‐based active power filters (APFs), which achieves dynamic reactive power and harmonic compensation. The most crucial problems in CHB‐APF control are the simultaneous requirements of both accurate harmonic current compensation and the dc‐link voltage stabilization among the H‐bridges, which is the prerequisite for the stable operation of CHB‐APF. To achieve dc‐link stabilization, a novel voltage balancing algorithm is proposed by splitting the dc‐link voltage control task into two parts, namely, the average voltage control and the voltage balancing control, where the sine and cosine functions of the phase angle of the fundamental component of the grid voltage are used, respectively. To ensure accurate phase tracking, a novel phase‐locked loop (PLL) is proposed by using the adaptive linear neural network (ADALINE), where the grid voltage background distortion is also taken into account. The superior performance of the ADALINE‐PLL is validated by comparison with the existing PLLs in literatures. Furthermore, the proportional‐resonant (PR) controller is used for the reference current tracking. A separate ADALINE algorithm is applied for reference current generation (RCG) for the CHB‐APF. The excellent performance of the ADALINE‐based RCG scheme is verified by comparison with the existing RCG schemes, namely, the low‐pass filter approach and the single‐phase p ? qmethod. The experimental results on the three modules CHB‐APF are presented, which verifies the effectiveness of the proposed control algorithms. Copyright © 2011 John Wiley & Sons, Ltd.     

An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Design for testability of high‐order OTA‐C filters

A study of oscillation‐based test for high‐order Operational Transconductance Amplifier‐C (OTA‐C) filters is presented. The method is based on partition of a high‐order filter into second‐order filter functions. The opening Q‐loop and adding positive feedback techniques are developed to convert the second‐order filter section into a quadrature oscillator. These techniques are based on an open‐loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth‐order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth‐order cascade, inverse follow‐the‐leader feedback (IFLF) and LF OTA‐C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation‐based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA‐C filters, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A novel induction generator system using bi‐directional PWM converter for small‐scale power applications

This paper presents a deadbeat current control structure for a bidirectional power flow pulse‐width modulation (PWM) converter connected to a stand‐alone induction generator (IG), which works with variable speed and different types of loads. Sensorless control of the IG, meaning stator voltage vector control without a mechanical shaft sensor, is considered to regulate both the IG line‐to‐line voltage and the DC‐bus voltage of the PWM converter. In the proposed system, a newly designed phase locked loop (PLL) circuit is used to determine the stator voltage vector position of the IG. A 2.2 kW laboratory prototype has been built to confirm the feasibility of the proposed method. The proposed cost‐effective IG system with a deadbeat current‐controlled PWM converter and capacitor bank requires only three sensors. Moreover, the required rating of the PWM converter becomes smaller due to the existence of the capacitor bank. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Compensation method of phase‐locked loop under unbalanced grid condition based on harmonic linearization

The voltage source converter (VSC) is often faced with unbalanced grid conditions that will degrade its performance because of the distorted current with a large amount of harmonics. One of the main parts of current distortion is the third‐order harmonics caused by the negative‐sequence voltage component at the fundamental frequency. The distorted output of the synchronous reference frame phase‐locked loop (SRF‐PLL) due to the unbalanced grid voltage is the main reason for the existence of the harmonics. This paper analyzes the mechanism of the generation of harmonics currents and proposes a compensation method for the PLL in VSCs based on the harmonic linearization method without changing the structure of SRF‐PLL. The proposed PLL can work properly under unbalanced grid conditions and has a good dynamic response. The third‐order current harmonics are reduced significantly by using the proposed PLL instead of the conventional SRF‐PLL without changing the current control strategy of VSC. The compensation method is verified by cycle‐by‐cycle circuit simulations and controller hardware‐in‐the‐loop experiments.     

High‐frequency measurements of the magnetoresistance effect of thin films

The ac magnetoresistance of thin films at frequencies up to 10 kHz was successfully measured. Patterned electrodes with mechanical flexibility were pressed onto the film surface by using a rubber pad. Induction noises were reduced considerably in comparison to the conventional four‐electrode method. A seven‐electrode system was developed to prevent high‐frequency induction noise, typically induced by leakage flux from the sample edges. It was found that the seven‐electrode system enables magnetoresistance measurements with little induction noise at frequencies up to 10 kHz. © 2000 Scripta Technica, Electr Eng Jpn, 132(2): 1–5, 2000     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process

For a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm² including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.