A low voltage, dynamic, noninverting, synchronous buck-boost converter for portable applications

With the increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices, efficient power management techniques are needed for longer battery life. Given the highly variable nature of batteries (e.g., 2.7-4.2 V for Li-ion), systems often require supply voltages to be both higher and lower than the battery voltage (e.g., power amplifier for CDMA applications), while supplying significant current, which is most efficiently generated by a noninverting buck-boost switching converter. In this paper, the design and experimental results of a new dynamic, noninverting, synchronous buck-boost converter for low voltage, portable applications is reported. The converter's output voltage is dynamically adjustable (on-the-fly) from 0.4 to 4.0 V, while capable of supplying a maximum load current of 0.65 A from an input supply of 2.4-3.4 V. The worst-case response time of the converter for a 0.4 to 4 V step change in its output voltage (corresponding to a 0.2 to 2 V step at its reference input) is less than 300 /spl mu/sec and to a load-current step of 0 to 0.5 A is within 200 /spl mu/sec, yielding only a transient error of 40 mV in the output voltage. This paper also presents a nonmathematical, intuitive analysis of the time-averaged, small-signal model of a noninverting buck-boost converter.     

Low voltage techniques [for micropower operational amplifiers]

A micropower operational amplifier is described that will operate from a total supply voltage of 1.1 V. The complementary class-B output can swing within 10 mV of the supplies or deliver /spl plusmn/20 mA with 0.4 V saturation. Common mode range includes V/SUP -/, facilitating single-supply operation. Otherwise, DC performance compares favourably with that of the LM108. An adjustable-output voltage reference is also presented that uses a new technique to eliminate the bow usually found in the temperature characteristics of the band-gap reference. Minimum supply is 1 V, and typical drift is 0.002 percent//spl deg/C.     

Monolithic analog multiplier-divider

The design of a precision general-purpose monolithic analog multiplier-divider based on the principle of the variable transconductance of bipolar transistors is described. The device has two new aspects: first, an eight-transistor multiplier-divider core, and second, an improvement in the accuracy and high-frequency behavior of the input and output circuits having monolithic conversion resistors. The transfer function /spl nu//SUB w/=/spl nu//SUB x//spl nu//SUB y///spl nu//SUB z/ is only dependent on external voltages. An advantage of the multiplier-divider over a multiplier with a fixed internal voltage reference is that the external signal voltages can be accurately related to the relevant reference voltage. Moreover, the additional divider input enlarges the application field. The maximum signal voltages are /spl plusmn/10 V. The untrimmed inaccuracy is typically 2 percent. The nonlinearity is /spl plusmn/0.1 percent. The bandwidth is 6.5 MHz, and the slew rate is 50 V//spl mu/s.     

A fast, latching comparator for 12 bit A/D applications

High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.     

On-panel output buffer with offset compensation technique for data driver in LTPS technology

To overcome the offset voltage (V/sub OS/) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-/spl mu/m LTPS technology. Using the offset compensation technique, the V/sub OS/ of output buffer can be controlled within /spl plusmn/100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.     

A high-voltage monolithic operational amplifier

An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.     

Performance, uniformity, and yield of 850-nm VCSELs deposited by MOVPE

Vertical-cavity surface-emitting lasers (VCSELs) emitting near 850 nm and fabricated with the metal-organic vapor phase epitaxy (MOVPE) epitaxial growth technique and a planar proton implant process have been demonstrated with excellent performance, uniformity, and yield across a 3-in wafer. Four thousand lasers were tested on a three-inch-diameter wafer, with a yield of 99.8%. This translates into a yield of 94% for fully functional 34/spl times/1 arrays. The average threshold current, threshold voltage, and dynamic resistance at 10 mA operating current were 3.07 mA, 1.59 V, and 34 ohms, respectively. Uniformity of better than /spl plusmn/9% in threshold current, /spl plusmn/1% in threshold voltage, and /spl plusmn/1.5% in maximum optical output power across a 34-element array was demonstrated.     

A five-terminal plus or minus 15-V monolithic voltage regulator

A five-terminal /spl plusmn/15-V monolithic voltage regulator has been developed that incorporates internal frequency compensation and internally provides a /spl plusmn/1 percent output voltage tolerance. In addition, a thermally symmetric layout design of the chip has been used to eliminate the detrimental effects of thermal feedback on the die and ensure that the complementary tracking output voltages will be independent of the power dissipation in the series pass power transistors. Complete fault protection is accomplished by providing the power transistors with good dc safe operating area, internally limiting the short circuit output currents, and accurately limiting the junction temperature to within 10/spl deg/C of the specified maximum limit. Also, a new Zener diode geometry is employed that significantly reduces the noise associated with the reference voltage.     

An integrated bandgap reference

Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load current. Low-frequency noise in a bandwidth 0.003 Hz相似文献   

Design considerations for linear optically coupled isolation amplifiers

A hybrid optically coupled isolation amplifier is described which optimizes DC performance, bandwidth, physical size, and cost. The design utilizes a blend of monolithic and hybrid technologies to achieve this unique set of characteristics. The development of the linear optical coupler is traced. Optical and electronic circuit techniques are presented that combine, for the first time, precision performance with miniature packaging. Optional connections allow unipolar/bipolar and inverting/noninverting operation with both voltage and current inputs. Typical performance, based upon production runs, includes: 1000 V isolation voltage, 10 nA offset current, 1 pA//spl deg/C offset drift, 0.3 /spl mu/A barrier leakage at 60 Hz, 0.05 percent nonlinearity, and a bandwidth of over 60 kHz.     

Large swing CMOS power amplifier

A CMOS class AB power amplifier is presented in which supply-to-supply voltage swings across low-impedance loads are efficiently and readily handled. The amplifier consists of a high-gain input stage and a push-pull unity-gain amplifier output stage. The amplifier dissipates only 7 mW of DC power and delivers 36 mW of AC power to a 300-/spl Omega/ load, using standard power supplies of /spl plusmn/5.0 V. Lower impedance loads can be driven to higher power levels, providing the internal current limiting level is not exceeded.     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.     

A single chip FSK modem

In the development of a fully LSI-designed single-chip 300-b/s asynchronous FSK modem, two `hard to beat' problems are: (1) to build both analog and digital circuits on-chip in-such a way that the modem performance is practically free from line noise and transmission distortion; and (2) to meet the requirement (CCITT V.21) of a +5 dBm level margin to discriminate carrier-on from carrier-off under the rigid operating conditions expected. It was found that a combination of high-gain limiter, digital PLL, and postdetection filter in the demodulator section was useful to solve the first problem. A combination of a stabilized rectifier and voltage reference generator contributed to the solution of the second problem. Measurements on chips indicated at /spl plusmn/12% isochronous distortion in the received signal level range of -5 to -45 dBm, a 10/SUP -5/ bit error rate at an SNR of 3 dB, and /spl plusmn/0.15 dB carrier detection level deviation over the temperature range from -20 to +100/spl deg/C within the supply voltage variations of /spl plusmn/10%. Switched-capacitor filters were used throughout the analog section. The device requires two power supplies, +12 and +5 V. The power consumption is 85 mW, and the chip size is 5.9/spl times/5.4 mm.     

CMOS digital duty cycle correction circuit for multi-phase clock

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50/spl plusmn/0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 /spl mu/m CMOS technology is used in this work.     

The uni-polarity phase-shifted controlled voltage mode AC-AC converters with high frequency AC link

A circuit configuration and circuit topological family of voltage mode ac-ac converters with high frequency ac links, which are based on forward converters, and a uni-polarity phase-shifted control strategy are proposed and deeply investigated. These kinds of converters consist of a input cycloconverter, a high frequency transformer, an output cycloconverter, input and output filters, and can transfer an unsteady ac voltage with a high harmonic into steady same-frequency ac sinusoidal voltage with a low harmonic. By using uni-polarity phase-shifted control strategy, output filtering inductance current is naturally commutated, and zero voltage switching of the output cycloconverter is realized. The converters' averaging model, the output characteristic curve, and design criteria for the key circuit parameters are given. The theoretical analysis and test result of 1kVA 220V /spl plusmn/ 10% 50Hzac/110V 50Hz ac prototype have shown that the converters have such advantages as high frequency electrical isolation, simple topology, two-stage power conversion (LFAC/HFAC/LFAC), bidirectional power flow, uni-polarity synchronized pulsewidth modulation waveform, high efficiency, high power density, high steady precision, low total harmonic distortion of the output voltage, strong adaptability to various loads, high line power factor, and low audio noise etc.     

Bow-tie retrodirective rectenna

A novel bow-tie retrodirective rectenna designed at 5.8 GHz is proposed. The new retrodirective rectenna combines a traditional rectenna with a retrodirective array. The new retrodirective rectenna array can automatically steer its main beam towards the power source and hence is not sensitive to the power incident angle changes. It can provide a constant DC output voltage within /spl plusmn/10/spl deg/ and 90% DC output voltage within /spl plusmn/30/spl deg/. The conversion efficiency of the arrays is 84% when the power density is 10 mW/cm/sup 2/.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

High-gain SiGe transimpedance amplifier array for a 12/spl times/10 Gb/s parallel optical-fiber link

A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 /spl mu/A/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12/spl times/10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools.     

A monolithic 16-channels analog array normalizer

A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages which are in the same ratios as the inputs with a peak amplitude controllable by the user. Response time is in the region of 1 /spl mu/s at full scale. The chip includes provisions for expansion to any number of channels. Operation is from supplies of /spl plusmn/3 to 15 V at a quiescent current of 125 /spl mu/A. Details of the design principles and peripheral circuitry are provided. Measurements of static accuracy and dynamic performance demonstrate that this approach may often simplify preprocessing of signal arrays in pattern-recognition applications.     

Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications

An integrated DC-DC hysteretic buck converter with ultrafast adaptive output transient response for reference tracking is presented. To achieve the fastest up-tracking speed, the maximum charging current control is introduced to charge up the output voltage with the maximum designed current. For down-tracking, the output is discharged by the load only to save energy. Although the converter works with hysteretic voltage mode control, an adaptive delay compensation scheme is employed to keep the switching frequency constant at 850 kHz to within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process. With an input voltage of 3 V, the output voltage can be regulated between 0.5 and 2.5 V. With a load resistor of 10 Omega, the up-tracking speed of the maximum reference step (0.5 to 2.5 V) is 12.5 mus/V. All design features are verified by extensive measurements.