双重掩蔽层实现石英晶体高深宽比刻蚀

由于石英晶体的刻蚀速率小,要实现石英晶体的高深宽比刻蚀,常用的光刻胶或金属掩膜不能满足工艺要求。提出使用双重掩蔽层的方法实现石英晶体的高深宽比刻蚀,即石英晶体和单晶硅键合,然后在单晶硅表面生长二氧化硅,二氧化硅作为刻蚀单晶硅的掩蔽层,单晶硅作为刻蚀石英晶体的掩蔽层。ICP刻蚀过程使用SF6作为刻蚀气体、C4H8作为钝化气体、He作为冷却气体。控制好气体的流量和配比,选择合适的射频功率,能刻蚀出深度为30μm,宽度为50μm的深槽。该工艺对开发新型石英晶体器件有积极的意义。     

多层高深宽比Si深台阶刻蚀方法

通过干法刻蚀,在Si衬底上制备出高深宽比的台阶结构是MEMS加工的基础工艺之一。多层台阶的刻蚀,是一种重要的折线断面制备方法,使实现结构更加复杂的器件成为可能。利用LPCVD生长1μm厚SiO2作为钝化层,围绕多层台阶掩膜的制备方法和移除方法展开实验,以3层台阶为例,开发出一套使用一块光刻版制造任意宽度的台阶掩膜的方法。该方法节约成本、操作简便、重复性好,为加工复杂的三维结构提供了一种新的手段。另外,针对在深刻蚀过程中残留的掩膜会破坏Si台阶完整性的问题,研究了刻蚀过程中SiO2掩膜的去除方法对台阶的表面形貌造成的影响。通过实验发现,采用干湿腐蚀结合的方法可以有效地去除台阶掩膜,获得良好的Si深台阶结构。     

采用CHF_3和O_2等离子体刻蚀PI的各向异性研究

研究了一种有效刻蚀聚酰亚胺(PI)的干法刻蚀方法,以金属铬为掩膜,刻蚀经涂胶并亚胺化而得到具有一定厚度的PI薄膜。利用反应离子刻蚀设备(RIE)将O2和CHF3按一定比例混合,适当调节刻蚀压力、气体比例、功率、时间等因素,可以得到侧壁和底面光洁、具有不同表面形貌的刻蚀结构。借助台阶仪和显微测量工具测定刻蚀样片,进一步得到不同工艺参数下刻蚀深宽比,并通过分析得出其他因素对PI刻蚀深宽比的影响趋势。该项研究避免了"微掩膜"效应所产生的表面粗糙问题,同时优化了刻蚀工艺,得到各向异性刻蚀的具体工艺参数,为PI不同应用目的选择刻蚀工艺提供了理论依据。     

MEMS THz滤波器的制作工艺

基于MEMS技术制作了太赫兹(THz)滤波器样品,研究了制作滤波器的工艺流程方案,其关键工艺技术包括硅深槽刻蚀技术、深槽结构的表面金属化技术、阳极键合和金-硅共晶键合技术。采用4μm的热氧化硅层作刻蚀掩膜,成功完成了800μm的深槽硅干法刻蚀;采用基片倾斜放置、多次离子束溅射和电镀加厚的方法完成了深槽结构的表面金属化,内部金属层厚度为3~5μm;用硅-玻璃阳极键合技术和金-硅共晶键合技术实现了三层结构、四面封闭的波导滤波器样品加工。测试结果表明,研制的滤波器样品中心频率138GHz,带宽15GHz,插损小于3dB。     

硅/玻璃键合技术在RF-MEMS开关制作中的应用

介绍了一种新的RF-MEMS开关制作工艺,利用静电键合技术将表面微加工工艺与体硅加工工艺结合在一起完成开关上下电极的组合;说明了如何在普通环境下进行图形对准;通过静电力的理论计算和键合试验,分析了铝台阶对硅/玻璃静电键合的影响,得出铝台阶厚度低于100nm时键合效果较好;对有无铝台阶时的静电键合电流特性进行比较,分析了硅/玻璃界面电荷分布及其运动情况,为RF-MEMS开关的设计与制作提供了有意义的参考。     

MEMS器件制造工艺中的高深宽比硅干法刻蚀技术

硅的高深宽比刻蚀技术是MEMS领域中的一项关键工艺。在硅片上形成高深宽比沟槽并拥有垂直侧壁结构是现在先进MEMS器件的一个决定性要求。本文分别介绍了国际上近年来使用F基和Cl2等离子体获得高深宽比的刻蚀方法并进行了比较,总结了各自的优缺点及适用范围。     

硅微机械加工技术

微机械的全称为微电子机械系统，是以微电子技术和微加工技术为基础的一项新技术。目前主要应用的是硅微加工方法。本书着重介绍了硅微加工技术中应用的各种方法，包括各向异性湿法化学腐蚀、硅片键合、表面微机械加工、硅的各向同性湿法化学腐蚀、微机械加工技术中干法等离子刻蚀技术、远程等离子腐蚀、高深宽比沟槽腐蚀、微型结构的铸模等内容。     

含TSV结构的3D封装多层堆叠Cu/Sn键合技术

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。     

二氧化硅光波导刻蚀参量及掩膜的优化

硅基二氧化硅光波导是光通信中的关键器件.采用光刻胶以及金属作为掩膜进行了反应离子刻蚀二氧化硅光波导的工艺研究,获得了刻蚀速率及刻蚀选择比相对各工艺参数变化的三维神经网络模型.利用一种新型的用于二氧化硅深刻蚀的复合双层掩膜结构,克服了许多单层掩膜自身的限制,并利用这一结构制作出低传输损耗的硅基二氧化硅波导.     

硅深刻蚀中掩蔽层材料刻蚀选择比的研究

基于硅的高深宽比微细结构是先进微器件的关键结构之一,在其加工工艺中,具有高选择比的掩蔽层材料是该结构实现的重要保证.研究了在感应耦合等离子体刻蚀过程中射频功率和气体流量对不同材料刻蚀性能的影响,获得了在SF6等离子体中Si,SiO2,MgO以及Al等材料的刻蚀速率,同时获得了在该等离子体中Si相对SiO2,MgO以及Al的选择比.通过比较研究,得到了硅深刻蚀中最佳的掩蔽层材料及刻蚀工艺参数.     

用于高灵敏度红外探测器的超薄硅膜的研制

超薄、平整的硅膜对于制作高灵敏度红外探测器是非常重要的。这种超薄硅膜的各向异性腐蚀技术，包括有机溶液EPW和无机溶液KoH及KoH IPA(异丙醇)。从腐蚀速率、腐蚀表面质量、腐蚀停特性、腐蚀边缘形貌及腐蚀工艺的角度分析比较了两种腐蚀系统，分别制作出了约1μm厚的平整超薄硅膜，并研究了不同掩膜材料在腐蚀液中的抗蚀性，为高灵敏度红外探测器的制作奠定了工艺基础。     

微加工工艺应力的喇曼在线测量

针对微加工工艺过程造成的残余应力,文中提出了喇曼在线测量方法,并对最常用的三种微加工工艺:淀积、腐蚀或刻蚀及键合进行了喇曼在线测量.测量结果与理论分析相符,淀积工艺中,氮化硅对硅片造成的残余应力比氧化硅造成的大,且氧化硅在硅衬底上形成的残余应力是压应力,氮化硅形成的是张应力;刻蚀工艺和键合工艺对硅片造成了相对较大的应力分布,且都为张应力,最大值超过300MPa.     

三维掩膜硅各向异性腐蚀工艺释放微悬空结构

提出了一种新颖的基于三维掩膜的硅各向异性腐蚀工艺,即利用深反应离子刻蚀、湿法腐蚀等常规体硅刻蚀工艺和氧化、化学气相沉积(CVD)等薄膜工艺制作出具有三维结构的氧化硅(SiO2)或氮化硅(Si3N4)薄膜,以该三维薄膜作为掩膜进行各向异性腐蚀,该工艺可以应用于MEMS微悬空结构的制作。利用该工艺成功地在单片n-Si(100)衬底上完成了一种十字梁结构的释放,并对腐蚀的过程和工艺参数进行了研究。     

Research progress of III-V laser bonding to Si

The vigorous development of silicon photonics makes a silicon-based light source essential for optoelectronics'' integration. Bonding of III-V/Si hybrid laser has developed rapidly in the last ten years. In the tireless efforts of researchers, we are privileged to see these bonding methods, such as direct bonding, medium adhesive bonding and low temperature eutectic bonding. They have been developed and applied to the research and fabrication of III-V/Si hybrid lasers. Some research groups have made remarkable progress. Tanabe Katsuaki of Tokyo University successfully implemented a silicon-based InAs/GaAs quantum dot laser with direct bonding method in 2012. They have bonded the InAs/GaAs quantum dot laser to the silicon substrate and the silicon ridge waveguide, respectively. The threshold current of the device is as low as 200 A/cm². Stevan Stanković and Sui Shaoshuai successfully produced a variety of hybrid III-V/Si laser with the method of BCB bonding, respectively. BCB has high light transmittance and it can provide high bonding strength. Researchers of Tokyo University and Peking University have realized III-V/Si hybrid lasers with metal bonding method. We describe the progress in the fabrication of III-V/Si hybrid lasers with bonding methods by various research groups in recent years. The advantages and disadvantages of these methods are presented. We also introduce the progress of the growth of III-V epitaxial layer on silicon substrate, which is also a promising method to realize silicon-based light source. I hope that readers can have a general understanding of this field from this article and we can attract more researchers to focus on the study in this field.     

Cryogenic etching of n-type silicon with p doped walls with the TGZM process through the Al/Si eutectic alloy

The dry etching of n-type silicon with p⁺ doped walls was studied with the cryogenic etching directly after the thermomigration process. The selectivity between n-type silicon and p⁺ doped silicon was first considered in SF₆/O₂ plasma. No selectivity was observed between these two zones. Thereafter, the capacity of the Al/Si eutectic alloy covered with a thin film of Al₂O₃ to play the role of hard mask for the etching was confirmed, always in the case of SF₆/O₂ plasma. Finally, the etching of 50 μm deep trenches through the Al/Si alloy was performed using three different types of process.     

Silicon raised strip waveguides based on silicon and silicon dioxide thermal bonding

Si raised strip waveguides on SiO/sub 2/ have been proposed and fabricated, which are based on silicon-on-insulator (SOI) material. In the waveguides, the SOI technique utilizes silicon and silicon dioxide thermal bonding and back-polishing. An anisotropic etchant is used to produce the trapezoidal Si raised strip waveguides by etching the Si film down to the SiO/sub 2/ etch-stop buried layer. The transmission losses of the Si waveguides are measured to be less than 0.2 dB/cm at the 1.3 /spl mu/m wavelength for the lowest mode TE-like mode.     

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

Non‐Close‐Packed Crystals from Self‐Assembled Polystyrene Spheres by Isotropic Plasma Etching: Adding Flexibility to Colloid Lithography

Hexagonally ordered arrays of non‐close‐packed nanoscaled spherical polystyrene (PS) particles are prepared exhibiting precisely controlled diameters and interparticle distances. For this purpose, a newly developed isotropic plasma etching process is applied to extended monolayers of PS colloids (starting diameters <300 nm) deposited onto hydrophilic silicon. Accurate size, shape, and smoothness control of such particles is accomplished by etching at low temperatures (?150 °C) with small rates not usually available in standard reactive ion etching equipment. The applicability of such PS arrays as masks for subsequent pattern transfer is demonstrated by fabricating arrays of cylindrical nanopores into Si.     

Gas-phase selective etching of native oxide

Gas-phase selective etching of native oxide film formed on a silicon surface is an essential requirement for ULSI process technologies. Ultraclear anhydrous hydrogen fluoride (AHF) gas and a corrosion-free system were developed for this etching process. The reaction mechanism of silicon oxide film with moistureless HF was investigated, and selective etching conditions were developed. The gas-phase selective etching of native oxide in an environment of strictly controlled AHF concentration in N₂ is described