An 800-MHz quadrature digital synthesizer with ECL-compatibleoutput drivers in 0.8 μm CMOS

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 μm triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9×6.7 mm². Power dissipation is 3 W at 800 MHz and 5 V     

A CMOS Quadrature Baseband Frequency Synthesizer/Modulator

A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 m CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4–2.4835 GHz ISM frequency band. This frequency synthesizer/modulator is a capable of frequency and phase modulation. The major components are: a quadrature direct digital synthesizer, digital-to-analog converters and lowpass filters. By programming the quadrature direct digital synthesizer, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The quadrature baseband direct digital synthesizer produces an 80 MHz frequency band. The quadrature baseband spectrum could be upconverted with off-chip mixers into the 2.4 GHz ISM frequency band. The chip has a complexity of 17,803 transistors with a die area of 24 mm² and a core area of 9 mm². The power dissipation is 496 mW at 3.3 V.     

A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).     

A 0.7-3 GHz GaAs QPSK/QAM direct modulator

A single chip I/Q direct modulator for use in digital radio links is presented. This device translates directly the phase and quadrature baseband signals to a microwave frequency that can be chosen between 700 MHz and 3 GHz avoiding the use of IF circuits. It is able to generate any type of digital modulation as QPSK, n-PSK, n-QAM, GMSK, etc., with band-limited spectrum. The bandwidth of the I/Q modulating signals is more than 500 MHz allowing the use of the circuit even in the highest capacity systems. The device has 120 components in a 2.2×2.4 mm chip and has been fabricated using 0.5 μm GaAs MESFET process     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

正交混频相位式激光测距方法与系统实现

针对传统的二次混频式激光测距仪鉴相精度不高,难于消除系统误差等问题,提出了正交混频相位激光测距法,利用成熟的正交调制技术进行激光光强的幅度调制,提高了基于二次混频原理的激光测距仪的鉴相精度,并且通过改变低频信号相位来获得两个相对很小的频差,易于消除系统附加相移,大大简化了二次混频式激光测距仪的硬件设计。详细阐述了基于正交混频相位测距方法的激光测距原型机设计要点。系统原型机设计方案采用了集成度很高的正交调制芯片完成,结构紧凑没有冗余元件。原型机实验精度达到±1.52mm,在62.5MHz频点下测相精度达到0.042°,并且可以很方便地通过加入多频调制的方法大大提高测量距离,是采用二次混频法进行相位激光测距的优秀解决方案。     

A high-frequency electronically tunable quadrature oscillator

An architecture composed of mutually regenerative oscillators is introduced. It has been used to design a low-noise high-frequency voltage-controlled oscillator (VCO) capable of producing two output signals in quadrature with essentially identical properties. The phase relation between the quadrature outputs is frequency dependent and extremely stable. A novel way of coupling the regenerative oscillators is suggested in order to improve the frequency stability of the coupled oscillator system. Results obtained from a test chip have verified the viability of the oscillator concept. The oscillator circuit has been realized in a medium-frequency bipolar process. The tuning range extends to 500 MHz. At an oscillation frequency of 200 MHz, measured phase noise was -121 dBc/Hz at 1-MHz distance from the carrier.<>     

基于ΣΔ调制技术的CPFSK调制芯片设计

采用ΣΔ调制技术的小数分频频率合成器设计了CPFSK调制电路,对调制电路的原理以及噪声性能进行了细致的分析。芯片集成了2RC波形成形电路、三阶单级ΣΔ调制器、双模分频器、鉴频鉴相器、电荷泵和压控振荡器,在四电平2RC-CPFSK调制时,16kHz的带宽内可以实现25.6kbps的信息速率传输。电路采用0.35μm标准CMOS工艺实现,调节片外电感,芯片最高工作频率可以到200MHz。     

Quadrature direct digital frequency synthesis using fine-grain angle rotation technique

An area- and power-efficient quadrature direct digital frequency synthesis technique called fine-grain angle rotation is presented. To reduce the large bitwidth requirement of the angle rotation, multiple start points are introduced and the angle rotation is applied to the remaining small angle. A prototype chip occupies 0.16 mm/sup 2/ in 0.25 /spl mu/m 1P5M CMOS technology and consumes 90 mW at 400 MHz clock frequency, which is a significantly improved performance compared to previous state-of-the-art chips.     

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channelapplications

The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-μm CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f_in=f _s/2) and sampling frequencies f_s up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f_s /4 over process, temperature, and power-supply variations. At maximum speed (f_s=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f_in=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm² of chip area     

A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner

A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

Feedback-induced noise in index-guided semiconductor lasers and its reduction by modulation

We report a reduction in feedback noise of 15?20 dB by direct modulation of the laser with a 2?5 mA modulation current. The reduction is almost independent of modulation frequency in the frequency range from 50 MHz to 200 MHz, but depends on the external cavity length. The external cavity lengths considered are 5?15 cm.     

一种高速捷变并行调制矢量信号源的FPGA实现

在信号调制过程中,为了缩短载波生成的捷变时间,分析了影响捷变时间的因素。提出了单频信号的并行合成结构,解决了载波频率受现场可编程逻辑门阵列( FPGA)时钟限制的问题。为了解决调制过程中采样频率受时钟约束的问题,给出了矢量信号的正交并行调制结构。通过在FPGA上编写Verilog代码实现了时钟频率为160 MHz、采样率为1.92 Gsample/s的并行矢量信号调制,载波频率为200~300 MHz可变,捷变时间小于35 ns。结果表明,并行载波生成和并行调制的方法在克服系统时钟约束方面有较强的实用性。     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

A 200-MHz complex number multiplier using redundant binaryarithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05×1.33 mm² using 0.8 μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz     

A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-/spl mu/m CMOS

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.     

A Si bipolar phase and frequency detector IC for clock extractionup to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >±100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2²³-1. A 0.9-μm 12-GHz f_T silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W     

Design of Broadband Highly Linear IQ Modulator Using a 0.5$mu$m E/D-PHEMT Process for Millimeter-Wave Applications

A broadband highly linear IQ modulator using a 0.5-mum enhancement/depletion-pseudomorphic high-electron mobility transistor process is presented in this letter. An innovative broadside/edge coupler is proposed to apply to the IQ modulator. The chip size is only 1times1 mm², including radio frequency and baseband PADs. The sideband and local oscillation suppressions of the modulator are better than -33 and -15 dBc, respectively. At a carrier frequency of 60 GHz with a 64 quadrature amplitude modulation (QAM) modulation, the modulator demonstrates an error vector magnitude of within 3%, and an adjacent channel power ratio of better than -40 dBc. To the best of the authors' knowledge, this work demonstrates the best modulation quality with a 64 QAM modulation up to 60 GHz among all the reported reflection-type IQ modulators.