共查询到18条相似文献,搜索用时 203 毫秒
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针对差分功耗分析(DPA)攻击的原理及特点,分析了高级加密标准(AES)的DPA攻击弱点,采用掩盖(Masking)的方法分别对AES算法中字节代换部分(SubBytes)及密钥扩展部分进行了掩盖,在此基础上完成了AES抵御DPA攻击的FPGA硬件电路设计。通过对该AES的FPGA电路的差分功耗攻击实验验证,该方法能够很好地抵抗DPA攻击。 相似文献
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针对高级加密标准(Advanced Encryption Standard,AES)算法需要兼容不同工作模式以及不同密钥长度的加密需求,提出全通用AES加密算法。该算法通过设计可调节密钥扩展模块和模式选择模块,实现128/192/256位宽的加密,支持ECB/CBC/CFB/OFB/CTR 5种工作模式。基于Xilinx公司的XC7VX690T FPGA综合仿真,资源消耗为1 947 Slices,最高工作频率为348.191 MHz。 相似文献
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一种密钥可配置的DES加密算法的FPGA实现 总被引:1,自引:1,他引:0
在传统的DES加密算法的基础上,提出一种对密钥实行动态管理的硬件设计方案,给出了其FPGA实现方法。通过对DES加密原理的分析,利用其子密钥的生成与核心算法相关性较弱的特点,对密钥进行重新配置。DES算法采用资源优先方案,在轮函数内部设置流水线架构,提高了整体处理速度;在FPGA上实现轮函数和密钥变换函数独立运算,减少了相邻流水线级间的逻辑复杂度,从而实现了DES算法在FPGA条件下的重构设计。最终通过对设计结果的功能仿真和测试分析,论证了整个设计的正确性。 相似文献
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为了实现家居和建筑自动化(HBA)的数据安全传输,在欧洲安装总线(KNX/EIB)标准协议引入加密和认证机制;使用迪菲赫尔曼(Diffie-Hellman)算法实现非对称密钥共享,高级加密标准(AES)实现数据加密,基于哈希算法的挑战握手认证协议实现设备认证,使用控制器协调密钥分享和设备认证过程。模拟实验表明,所提方法在空间和时间上都是可行的,比其他改进方法更容易实现,操作更简单,能够保证数据的安全。 相似文献
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实现欧洲/电气安装总线协议数据加密和设备认证的方法 总被引:2,自引:0,他引:2
《计算机应用》2014,(3)
为了实现家居和建筑自动化(HBA)的数据安全传输,在欧洲安装总线(KNX/EIB)标准协议引入加密和认证机制;使用迪菲-赫尔曼(Diffie-Hellman)算法实现非对称密钥共享,高级加密标准(AES)实现数据加密,基于哈希算法的挑战握手认证协议实现设备认证,使用控制器协调密钥分享和设备认证过程。模拟实验表明,所提方法在空间和时间上都是可行的,比其他改进方法更容易实现,操作更简单,能够保证数据的安全。 相似文献
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现代鉴别技术,涉及对秘密(也就是密钥)的知识检测,可用合适的算法防止密码被破解,AES算法是现在公认的最有安全度和最有效率的算法。本文首先分析了对称密码和公钥密码及其相应的鉴别模型;然后给出了高级加密标准(AES)算法在PIC单片机上的优化,并进行了仿真;最后对AES加密方案的性能做了进一步的分析;在对加密时间要求不高,并且加密数据量很小的场合,使用8位单片机的软件进行优化和实现,可以简化电路,降低成本和功耗。 相似文献
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ECRYPT项目中的流密码LEX算法中每组AES加密过程使用相同的加密密钥,这导致其易受到滑动攻击。利用AES的密钥扩展算法改进了流密码LEX算法的密钥采用方案,改进后算法能够有效地抵抗滑动攻击。 相似文献
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Today most research involving the execution of the Advanced Encryption Standard (AES) algorithm falls into three areas: ultra-high-speed encryption, very low power consumption, and algorithmic integrity. This study’s focus is on how to lower the power consumption of an FPGA-based encryption scheme with minimum effect on performance. Three novel FPGA schemes are introduced and evaluated. These schemes are compared in terms of architectural and performance differences, as well as the power consumption rates. The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput. 相似文献
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This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key. 相似文献
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针对当前一类基于混沌系统的图像加密算法的应用进行研究,提出了一种五维细胞神经网络和AES(高级加密标准)加密算法相结合的超混沌图像加密算法。该方法定义了五个数和提取一个与明文像素值相关的参数作为密钥,通过细胞神经网络生成的超混沌序列作为AES加密算法的目标密钥;将明文与目标密钥进行异或处理;将目标密钥代入算法进行若干次AES加密算法进行加密得到密文。通过实验仿真表明,该算法能较好地抵抗差分攻击、统计特性分析等,而且还能有效抵抗明文攻击,加密效果较好。 相似文献
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Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power. 相似文献
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针对AES算法的特点,提出一种适用于在FPGA上实现的快速加解密资源共享的AES算法。对传统的AES加解密的s_box进行变换,使用一张查找表实现了加解密过程的资源共享,有效的节省了硬件实现面积。并对AES加解密的列混合变换进行了改进,从而达到资源共享,节省资源。本方案对轮密钥扩展,列混合变换及其逆变换等操作进行了优化处理,并在加密计算及解密计算中对S-盒,列混合变换等关键计算部件进行了复用,并且采用AES轮内流水结果和密钥并行处理,可在一块芯片上同时支持128位、192位、256位三种密钥长度的加解密算法。实验结果表明本设计相比于其他设计具有更高的性能。 相似文献