Parameterized physical compact thermal modeling

This paper presents a compact thermal modeling (CTM) approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing a CTM example with a BCI model for a benchmark ball grid array single-chip package under the same standard set of boundary conditions. In essence, the presented CTM method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging and three-dimensional integration.     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

Double-sided cooling for high power IGBT modules using flip chiptechnology

A new technique for the packaging of IGBT modules has been developed. The components are sandwiched between two direct bond copper (DBC) substrates with aluminum nitride. Wire bonds are replaced with flip chip solder bumps, which allows cooling of components on both sides. Microchannel heat sinks are directly integrated in the package to decrease the thermal resistance of the module. Thus, a very compact module with high thermal performance is obtained. A prototype with two insulated gate bipolar transistors (IGBTs) and four diodes associated in parallel was realized and tested. In this paper, the innovative packaging technique is described, and results of thermal tests are presented     

Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment     

Compact modeling of thermal noise in the MOS transistor

Although some of the recently proposed compact models for thermal noise in MOS transistors exhibit a good match with experimental data, we believe most of the existing compact models suffer from incorrect physical assumptions or modeling (e.g., absence of carrier heating, incorrect modeling of velocity saturation effect, wrong modeling of diffusivity, etc.). This brief presents a new, completely analytical thermal noise model based on consistent physical assumptions.     

Improved compact thermal model for studying 3-D interconnect structures with low-k dielectrics

Compact thermal modeling is gaining significance as interconnect feature sizes continue to shrink, requiring increased computation times for full-field multi-scale simulations. Improved and expanded uses of an existing compact thermal modeling approach found in Gurrum et al. [A compact approach to on-chip interconnect heat conduction modeling using the finite element method, ASME J. Electron. Packaging (2007), accepted], Gurrum et al. [A novel compact method for thermal modeling of on-chip interconnects based on the finite element method, ASME, EEP 3, Electron. Photon. Packing Electr. Syst. Photon. Des. Nanotechnol. (2003) 441-445] are presented here. The first improvement rectifies a singularity that occurs in the previous compact model. This change allows for greater flexibility in mesh application, and a greater number of structures that can be analyzed. This work focuses on the application of the compact thermal model to two interconnect structures. The first geometry [S. Im, N. Srivastava, K. Banerjee, K. Goodson, Scaling analysis of multilevel interconnect temperatures for high performance ICS, IEEE Trans. Electron. Dev. 52 (12) (2005) 2710-2719] is a typical interconnect structure based on the ITRS 65 nm technology node. A new transient compact model was applied to another geometry [J. Zhang, M. Bloomfield, J. Lu, R. Gutmann, T. Cale, Thermal stresses in 3D IC inter-wafer interconnects, Microelectron. Eng. 82 (3-4) (2005) 534-547], which is a more advanced technology with a through-the-die via structure. The second improvement of the compact model is extending the steady state finite element based model into a transient version. Full-field simulations have very large storage and memory requirements for transient analysis of complex structures. The advantage of this compact model is that in addition to increased efficiency, the methodology and implementation is similar to a traditional finite element analysis (FEA).     

Compact thermal models for internal convection

Objects undergoing heat transfer by convection internally, i.e., not at their boundaries, need special care in their modeling. An extension of the general formulation made earlier for compact thermal models is discussed here in order to cover the case of internal forced convection problems such as micro-channels. The single resistor model based on the heat transfer coefficient h is replaced with a compact model linking all relevant nodes using h as well as fluid thermal capacitance and inertia, such as to satisfy thermodynamic constraints derived earlier for conduction compact models.     

Thermal management of power electronics modules packaged by a stacked-plate technique

The research presented in this paper is part of a multidisciplinary research program of the Center for Power Electronics Systems at Virginia Tech. The program supported by the Office of Naval Research focuses on the development of innovative technologies for packaging power electronics building blocks. The primary objective of this research is to improve package performance and reliability through thermal management, i.e., reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thermal modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.     

Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.     

Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

Thermal compact modeling of parallel plate heat sinks

Growing complexity of electronic systems has resulted in an increased computational effort in CFD modeling of electronic systems. To reduce the computational effort, one or several heat sinks can be represented by a compact "porous block" model, with an effective thermal conductivity and pressure loss coefficient. In this study of parallel plate heat sinks in laminar forced convection, a methodology is developed to rigorously determine the thermal properties of compact heat sink models that provide a high level of accuracy. The results of an extensive set of CFD simulations for a three heat sink channel covering two distinct heat sink geometries, air velocities from 0.25 m/s to 2 m/s and various spacings between the heat sinks, were used to create and evaluate the fidelity of compact models. The results of this study establish the validity and value in using the porous block compact model representation for noncritical heat sinks in an electronic assembly. The results also reveal that a location-independent porous-block representation can yield excellent agreement in the prediction of the thermal characteristics of state-of-the-art heat sinks.     

A review of compact modeling for phase change memory

Phase change memory(PCM)attracts wide attention for the memory-centric computing and neuromorphic comput-ing.For circuit and system designs,PCM compact models are mandatory and their status are reviewed in this work.Macro mod-els and physics-based models have been proposed in different stages of the PCM technology developments.Compact model-ing of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical,thermal and phase transition dynamics as well as their interactions.Realizations of the PCM operations including threshold switching,set and reset programming in these models are diverse,which also differs from the perspective of circuit simulations.For the purpose of efficient and reliable designs of the PCM technology,open issues and challenges of the compact modeling are also discussed.     

A simple 1-D finite elements approach to model the effect of PCB in electronic assemblies

In this paper, a simple method to describe the effect of Printed Circuit Board (PCB) and environment on the thermal behavior of packaged devices is addressed. This approach aims at exploiting the benefit of compact thermal models, which are necessarily one-dimensional, together with the advantage of Finite Element (FE) modeling, which retains all the three-dimensional geometrical details, only in the regions of the model that must be accurately described. The main focus is on correct modeling of long power pulses for subsequent electro-thermal and thermo-mechanical analysis at chip level.     

硅热流量传感器封装的热模拟分析

针对硅热流量传感器的封装,给出了其一维简化理论模型,并采用有限元分析工具ANSYS/FLOTRAN,建立了该封装结构的热模型．模拟结果显示,该封装后的传感器的温度场与未封装传感器相似,证明陶瓷封装结构是可行的;同时比较了封装前后传感器性能的差异,并进一步分析了传感器的热性能和其特征尺寸的关系．该模型的建立,可以减少大量的模拟分析过程,减小计算量,研究结果将为该传感器封装的进一步优化设计提供理论参考和依据．     

Compact thermal networks for modeling packages

In this paper, thermal networks for modeling packages are rigorously introduced. A multipoint moment matching method for state space reduction of these discretized thermal networks is formulated. In this manner reduced thermal networks are derived that can be used as boundary condition independent compact thermal models of packages. This algorithm is successfully applied to the detailed analysis of an idealized ball grid array package.     

A study of compact thermal model topologies in CFD for a flip chipplastic ball grid array package

A previously validated detailed model of a 119-pin flip-chip plastic ball grid array (FC-PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, two compact models mere derived, a two-resistor model (created using the JEDEC-standard based computational approach), and a multiresistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multiresistor model provided the same predictive estimates (within 5%) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks     

Design and analysis of wafer-level CSP with a double-pad structure

Wafer level chip scale packaging (WLCSP) is very promising for the miniature of packaging size, the reduction of manufacturing cost, and the enhancement of the package's performance. However, the long-term board level reliability of integrated circuit (IC) devices using wafer level packaging with large distances from neutral point (DNP) is still not fully solved. This research proposes a novel, alternative WLCSP design for facilitating higher board level reliability. The main feature of the novel WLCSP is basically in its double-pad structure (DPS) design in the interface between solder joints and silicon chip. To characterize the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear finite element (FE) modeling technique is employed. Based on the FE modeling, the numerical accelerated thermal cycling (ATC) test is performed under the JEDEC temperature cycling specification. The validity of the proposed FE modeling is verified by using an optical measurement method Twyman-Green interferometer. By the derived incremental equivalent plastic strain, the cumulative cycles to failure in solder joints associated with these four WLCSP are assessed based on a modified Coffin-Manson relationship. The modeled fatigue life is compared against the experimental results that adopt a two-parameter Weibull distribution to characterize cycles-to-failure distribution. For comparison, the investigation also involves several existing types of WLCSP, including the conventional (C-WLCSP), the copper post (CP-WLCSP), and the polymer post (PP-WLCSP), and solder joint reliability performance among these WLCSP packages is extensively compared. The results demonstrate that the DPS-WLCSP design not only has potential for enhancing the corresponding solder joint reliability but is also particularly effective in manufacturing process and cost. And finally, some reliability-enhanced design guidelines are provided through parametric design of the DPS.     

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.     

Thermal modeling and performance of high heat flux SOP packages

This paper explores the thermal challenges in advanced system-on-package (SOP) electronic structures, as well as candidate thermal solutions for these highly demanding cooling needs. The heat fluxes on the active surfaces are expected to approach 100 W/cm/sup 2/. The impact of this high flux is exacerbated by the relatively low thermal conductivity of the organic materials in SOP packaging. Detailed three-dimensional (3-D) finite element simulations were used to study the temperature distributions in a typical SOP package, and to provide guidance for the development and implementation of "compact thermal models". These models were used to evaluate and compare the performance of various thermal technologies and to establish the most promising thermal management alternatives. The use of direct liquid cooling, by immersion of the components in inert, nontoxic, high dielectric strength perfluorocarbon liquids was seen to provide effective cooling over a range of anticipated SOP power dissipations.     

压接式GCT封装的热特性分析

电力半导体器件的散热性能和热可靠性与其封装结构密切相关,选择合适的封装结构对改善器件的散热性能和提高热可靠性非常重要。文中根据压接式GCT器件封装结构特点,采用ANSYS软件利用有限元法分析了单芯片封装和多芯片封装结构的温度及热机械应力分布,并与常规的焊接式封装进行了对比。结果表明,压接式封装结构的散热效果比焊接式封装结构稍差,但其芯片上产生的热机械应力明显减小。多芯片封装采用常规的风冷散热器时芯片温度已经超过了器件的安全工作温度(125℃),应该采用热管散热器才能保证器件可靠地工作。