Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Modelling the effect of uneven PWB surface on stencil bending during stencil printing process

In the mass assembly of today’s electronic circuits, solder paste is first printed onto the surface of the assembly boards through a metal mask called a stencil. The possible surface differences in level on the PWB, e.g. marking stickers or other protruding objects keep the stencil away from the PWB during stencil printing, can cause excessive printed volume of the solder paste, and solder bridges or other soldering failures can occur after reflow soldering. If these differences in level are not too high or they are sufficiently far from the soldering pads in lateral direction, the stencil can bend down to the pad during stencil printing and the volume of the deposited solder paste will be as expected.In our research a Finite Element Model (FEM) was created to investigate the stencil deformation and to determine the necessary distance between the pads and the local differences in level to achieve complete stencil contact to the PWB. A simple deformation measuring set-up was designed and fitted together to experimentally determine the mechanical parameters of the stencil and the squeegee, which were necessary for the FEM. PWB surface differences in level in the range of 0–90 μm and stencil foil thicknesses varying between 75 and 175 μm were inserted into the FEM as geometrical parameters and simulations were executed to calculate the minimum distances which are necessary to achieve perfect stencil contact to the PWB. The FEM was verified by comparing simulation results to experimental results obtained by real stencil printing.     

Reliability investigations on LIFT-printed isotropic conductive adhesive joints for system-in-foil applications

The reliability of a commercially available isotropic conductive adhesive (ICA) deposited via laser induced forward transfer (LIFT) printing is reported. ICAs are particularly important for surface mount device (SMD) integration onto low-cost, large-area system-in-foil (SiF) applications such as radio frequency identification (RFID) transponder tags. For such tags, and for SiF in general, the reliability of the printed interconnects under harsh circumstances is critical. In this study, the reliability of surface mounted resistors bonded onto screen-printed conductive circuitry on polymer foil was assessed. The prepared samples were subjected to thermal shock testing (TST), accelerated humidity testing (AHT) and flexural testing, while electrical measurements were conducted at regular intervals. Die shear testing was performed to evaluate the bond strength. The reliability characteristics of the LIFT-printed samples were benchmarked against current industry standard stencil printing process. Finally, the applicability of the LIFT–ICA process for practical applications is demonstrated using RFID transponder integration and testing.     

焊膏印刷技术前景展望

元器件的小型化及细间距化带来电子产品的高密度组装,其次高的组装效率及智能化工艺控制导致SMT发生巨大变化.从模板设计、焊膏选择及印刷工艺参数控制等方面对焊膏印刷技术未来发展进行了简单的阐述.     

Polymer film deposition with fine pitch openings by stencil printing

It is confirmed that stencil printing with a novel developed printable polyimide paste can be used for polymer film deposition on LSI wafers. A thick polyimide film with openings for solder ball bumping can be deposited on all of the LSIs on a wafer by stencil printing at one time. This stencil printing process does not need an expensive lithography process, providing cost-effective wafer-level chip scale packages (WLCSPs). In this study, a novel polyimide paste was tailored to have a higher thixotropy ratio than conventional printable polyimide materials. The novel printable polyimide paste shows that the viscosity ratio of more than 3.5 at the shear rate of 1 to 10 s⁻¹ and that the viscosity increases rapidly after the shear rate is lowered. Fine spaces of 40 μm between 250 μm openings were obtained for 10 μm thick polyimide films on Si wafers. It has been also confirmed that the new paste shows the variation range of 30 μm at the opening size of 385 μm within 100 continuously printed wafers. Even after the new paste was shear-thinned repeatedly, rheological behavior of the new paste was not changed. This robustness leads to higher efficiency of the materials for mass-producing. From the reliability viewpoint of the printed polyimide films, no peelings were observed on plasma-CVD SiN films after the pressure cooker test under the condition of 127 °C and 0.25 MPa with the humidity of 100% for 300 h. The optimal stencil printing process using the novel developed paste will lead to significant cost reduction of a patterned polymer deposition process. Finally, WLCSPs using the stencil printing of the new polyimide paste have been demonstrated for SRAM LSIs on 8-in. wafers.     

Stencil‐based 3D facial relief creation from RGBD images for 3D printing

Three‐dimensional (3D) selfie services, one of the major 3D printing services, print 3D models of an individual's face via scanning. However, most of these services require expensive full‐color supporting 3D printers. The high cost of such printers poses a challenge in launching a variety of 3D printing application services. This paper presents a stencil‐based 3D facial relief creation method employing a low‐cost RGBD sensor and a 3D printer. Stencil‐based 3D facial relief is an artwork in which some parts are holes, similar to that in a stencil, and other parts stand out, as in a relief. The proposed method creates a new type of relief by combining the existing stencil techniques and relief techniques. As a result, the 3D printed product resembles a two‐colored object rather than a one‐colored object even when a monochrome 3D printer is used. Unlike existing personalization‐based 3D printing services, the proposed method enables the printing and delivery of products to customers in a short period of time. Experimental results reveal that, compared to existing 3D selfie products printed by monochrome 3D printers, our products have a higher degree of similarity and are more profitable.     

Cover Picture: High Definition Digital Fabrication of Active Organic Devices by Molecular Jet Printing (Adv. Funct. Mater. 15/2007)

A new method for direct patterning of organic optoelectronic/electronic devices using a reconfigurable and scalable printing method is reported by Vladimir Bulovic and co‐workers on p. 2722. The printing technique is applied to the fabrication of high‐resolution printed organic light emitting devices (OLEDs) and organic field effect transistors (OFETs). Remarkably, the final print‐deposited films are evaporated onto the substrate (rather than solvent printed), giving high‐quality, solvent‐free, molecularly flat structures that match the performance of comparable high‐performance unpatterned films. We introduce a high resolution molecular jet (MoJet) printing technique for vacuum deposition of evaporated thin films and apply it to fabrication of 30 μm pixelated (800 ppi) molecular organic light emitting devices (OLEDs) based on aluminum tris(8‐hydroxyquinoline) (Alq₃) and fabrication of narrow channel (15 μm) organic field effect transistors (OFETs) with pentacene channel and silver contacts. Patterned printing of both organic and metal films is demonstrated, with the operating properties of MoJet‐printed OLEDs and OFETs shown to be comparable to the performance of devices fabricated by conventional evaporative deposition through a metal stencil. We show that the MoJet printing technique is reconfigurable for digital fabrication of arbitrary patterns with multiple material sets and high print accuracy (of better than 5 μm), and scalable to fabrication on large area substrates. Analogous to the concept of “drop‐on‐demand” in Inkjet printing technology, MoJet printing is a “flux‐on‐demand” process and we show it capable of fabricating multi‐layer stacked film structures, as needed for engineered organic devices.     

High-Density Solder Bump Interconnect for MEMS Hybrid Integration

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

电子组装中胶黏剂及其涂覆工艺的选择(待续)

胶黏剂在混装及双面回流焊接工艺中主要是把元器件固定于电路板底面,以便进行波峰焊或双面回流焊工艺.常用的胶黏剂涂覆方法包括针转移法、点涂法和丝网印刷法/模板印刷法.模板印刷法近年来在大批量高速流水线生产中得到了较为广泛的应用.主要介绍了胶黏剂的涂覆工艺及选择、胶黏剂的性能及选择和胶黏剂的相关工艺设计,并对其进行了较为详细的分析.     

电子组装中胶黏剂及其涂覆工艺的选择（待续）

胶黏剂在混装及双面回流焊接工艺中主要是把元器件固定于电路板底面,以便进行波峰焊或双面回流焊工艺.常用的胶黏剂涂覆方法包括针转移法、点涂法和丝网印刷法/模板印刷法.模板印刷法近年来在大批量高速流水线生产中得到了较为广泛的应用.主要介绍了胶黏剂的涂覆工艺及选择、胶黏剂的性能及选择和胶黏剂的相关工艺设计,并对其进行了较为详细的分析.     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Direct gravure printing (DGP) method for printing fine-line electrical circuits on ceramics

The tendency toward higher packing densities and higher frequencies for telecommunication devices based on ceramic technology requires smaller dimensions for electrical wiring. Electrical thick-film circuits for ceramic and LTCC-substrates have, up to now, been printed with screen printing, where the printing lines width limit is about 125 /spl mu/m in mass production. A silicone polymer direct gravure printing (Si-DGP) process has been developed to perform smaller dimensions, down to 20 /spl mu/m lines width, for electrical circuitry. In the DGP process, the conductor paste is doctored to the grooves of the gravure and then it is pressed against the substrate. The paste is, thus, printed directly onto the substrate from the patterned gravure. The results showed that, using the DGP process, it was possible to print conductor lines down to 20 /spl mu/m in width. It was also noted that a 100% transfer of paste from the grooves of the gravure could be obtained with commercial pastes using the silicone polymer gravure. A dried thickness of up to 28 /spl mu/m was measured for the narrowest lines. Also conductor lines printed by the Si-DGP method were embedded inside LTCC-module.     

Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.     

Critical variables of solder paste stencil printing for micro-BGA and fine-pitch QFP

Stencil printing continues to be the dominant method of solder deposition in high-volume surface-mount assembly. Control of the amount of solder paste deposited is critical in the case of fine-pitch and ultrafine-pitch surface-mount assembly. The process is still not well understood as indicated by the fact that industry reports 52-71% surface-mount technology (SMT) defects are related to the solder paste stencil printing process. The purpose of this paper is to identify the critical variables that influence the volume, area, and height of solder paste deposited. An experiment was conducted to investigate the effects of relevant process parameters on the amount of solder paste deposited for ball grid arrays (BGAs) and quad flat packages (QFPs) of five different pitches ranging from 0.76 mm (30 mil) to 0.3 mm (12 mil). The effects of aperture size, aperture shape, board finish, stencil thickness, solder type, and print speed were examined. The deposited solder paste was measured by an inline fully automatic laser-based three-dimensional (3-D) triangulation solder paste inspection system. Analysis of variance (ANOVA) shows that aperture size and stencil thickness are the two most critical variables. A linear relationship between transfer ratio (defined as the ratio of the deposited paste volume to the stencil aperture volume) and area ratio (defined as the ratio of the area of the aperture opening to the area of the aperture wall) is proposed. The analysis indicates that the selection of a proper stencil thickness is the key to controlling the amount of solder paste deposited, and that the selection of maximum stencil thickness should be based on the area ratio. The experimental results are shown to be consistent with a theoretical model, which are also described.     

细间距漏印模板与焊膏

在总结本厂苛产品试制工艺的基础上，就细间距的焊膏漏印模板的几种加工方法，模板开口模板开口侧壁的形状与要求进行了比较与说明，同时就细间距技术对焊膏的内在质量要求和工艺性要求进行了概述和总结。     

Automated fabrication of hybrid printed electronic circuits

Printed electronics offer great potential for new applications such as Internet of Things devices and wearables. However, to date, only a limited number of electronic functions and integration densities can be realised by printing processes. Hence, hybrid printed electronic circuits are actually created by mounting silicon electronic components. Since both printed materials and processes are continuously evolving, an accompanying structured development methodology is required. This paper highlights a digital workflow from design to automated fabrication using the example of a demonstrator circuit. A multi-layer vector ink-jet printing process to print electronic devices onto foil substrates with three functional inks is presented. This printing process is improved using a newly set-up printing system: Integrating a piezo print head into the path planning of the printing system and its control as a virtual stepper axis enable highly precise vector printing. This leads to printed resistors with low tolerances. Adaptations of surface mount technology for assembling silicon electronic components onto printed foil substrates are discussed. Finally, image processing methods to cope with deformations of the flexible foil substrates in the fabrication process are introduced.