A triple-well resonant tunneling diode for multiple-valued logicapplication

A resonant tunneling diode with four potential barriers and three quantum wells was fabricated and applied to multiple-valued logic. The diode exhibited significant double negative resistance characteristics and operated as a triple stable device with a single voltage between 180 and 230 K     

Modified super pass gate for multiple-valued logic circuits

A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique     

A novel A/D converter using resonant tunneling diodes

A large-signal resonant tunneling diode (RTD) model is used to simulate the performance of a 2-b A/D converter. Results from the theoretical analysis, the breadboard circuit demonstration, and the SPICE3 simulation are discussed. It is shown that the unique folding characteristics of the vertically integrated RTD greatly reduce the complexity of the A/D converter circuit, making analog-to-digital conversion at tens-of-gigahertz rates possible     

Multi-threshold threshold logic circuit design using resonant tunnelling devices

A novel and extremely compact circuit topology able to implement a generalised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.     

Resonant tunneling devices with multiple negative differential resistance and demonstration of a three-state memory cell for multiple-valued logic applications

A new resonant-tunneling (RT) functional device with two peaks in the current-voltage (I-V) characteristic has been demonstrated. Contrary to conventional RT devices, the peaks are obtained using a single resonance of the quantum well. The peak's separation is voltage tunable and the peak currents are nearly equal, which is important for a variety of device applications. Using a single device, a three-state memory cell has been implemented.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates     

Compact multiple-valued multiplexers using negative differentialresistance devices

Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTD's) and heterojunction bipolar transistors (HBT's) with the folded I-V characteristic (NDR characteristic) of the RTD's providing the compact logic implementation and the HBT's providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHET's) and resonant tunneling bipolar transistors (RTBT's) is also demonstrated     

Tri-state logic using vertically integrated Si-SiGe resonant interband tunneling diodes with double NDR

A vertically integrated npnp Si-based resonant interband tunneling diode (RITD) pair is realized with low-temperature molecular beam epitaxy by stacking two RITDs with a connecting backward diode between them. The current-voltage characteristics of the vertically integrated RITD pair demonstrates two sequential negative differential resistance regions in the forward-biasing condition. Tri-state logic is demonstrated by using the vertically integrated RITDs as the drive and an off-chip resistor as the load.     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

CMOS implementation of a multiple-valued logic signed-digit fulladder based on negative-differentiaI-resistance devices

This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-μm CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 μm² and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation     

Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described     

Folded gate—A novel logic gate structure

We propose a new logic gate structure which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This "folded" gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher then the speed of conventional direct-coupled field-effect transistor logic (DCFL), and a larger voltage swing.     

A novel amorphous silicon doping superlattice device with doubleswitching characteristics for multiple-valued logic applications

An amorphous silicon doping superlattice device with different period lengths is developed, providing a double switching characteristic that has been demonstrated to yield multiple stable states for multiple-valued logic applications. Unlike those of conventional switching devices, the switching characteristics of the present device are caused by avalanche multiplication and a barrier-lowering effect. A tristate memory cell using this device is proposed and discussed     

Coupled-quantum-well field-effect resonant tunneling transistor formulti-valued logic/memory applications

A vertical field-effect resonant tunneling transistor is demonstrated consisting of a triple-barrier, double-well resonant tunneling diode (3bRTD) that can be depleted by the action of side gates. The 3bRTD features a double peak current-voltage characteristic in which the second valley current is less than the first valley current. Combination of the resonant tunneling transistor and a constant current load is shown to yield both binary and ternary logic and memory functions     

A novel resonant gate driver for high frequency synchronous buckconverters

This paper introduces a new resonant gate driver for both the top and bottom switches of a synchronous buck converter. A coupled inductor is used to reduce the size as well as to transfer energy between the top and bottom gate driving. A possible semiconductor integration approach is proposed for this resonant gate driver based on a self-adaptive control method. Theoretical analysis, simulation and experimental results prove that the proposed driver can greatly reduce the gate driving loss and that it is well suited to high-frequency applications     

A novel productivity-driven logic element for field-programmable devices

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.     

A self-latching A/D converter using resonant tunneling diodes

A high-speed analog-to-digital (A/D) converter based on the resonant tunneling diode (RTD) is described. This A/D converter takes advantage of the folding characteristic of the RTD to reduce circuit complexity. The speed of the A/D converter is improved by the fast latching action of the RTD digitizer. Simulations show that the 4-B A/D converter can have a sampling rate of several gigahertz     

Characterising gate dielectrics in high mobility devices using novel nanoscale techniques

Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.     

A novel InGaP/GaAs S-shaped negative-differential-resistance (NDR)switch for multiple-valued logic applications

In this paper, a novel InGaP/GaAs multiple S-shaped negative-differential-resistance (NDR) switch based on a heterostructure-emitter bipolar transistor (HEBT) structure is fabricated and demonstrated. An interesting multiple NDR phenomenon resulting from an avalanche multiplication and successive two-stage barrier lowering process is observed under the inverted operation mode. The three-terminal-controlled and temperature-dependent NDR characteristics are also investigated. In addition, a typical transistor performance is found under the normal operation mode. Consequently, owing to the presented different stable operation points and transistor action, the studied device shows a good potential for multiple-valued logic and analog amplification circuit applications