A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.     

The threshold-voltage model of MOSFET devices with localizedinterface charge

A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases     

A small geometry MOSFET model for CAD applications

A d.c. model for the CAD analysis of small geometry MOSFET's is presented. It includes the drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena. A single current expression valid in continuous way over the entire range of operation, including the subthreshold and the saturation regimes, is provided.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

A new 2-D analytic threshold-voltage model for fully depletedshort-channel SOI MOSFET's

The exact solution of the 2-D Poisson equation for fully depleted SOI MOSFETs is derived by using a three-zone Green's function solution technique. Based on the derived 2-D potential distribution, the front and back surface potential distributions in the Si film are analytically obtained and their accuracies are verified by 2-D numerical analysis. The calculated minimum surface potential and its location are used to analyze the drain-induced barrier-lowering effect and further to develop an analytic threshold-voltage model. Comparisons between the developed analytic threshold-voltage model and the 2-D numerical analysis are made. It is shown that excellent agreements are obtained for wide ranges of device structure parameters and applied biases     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

A 2-D analytic model for the threshold-voltage of fully depletedshort gate-length Si-SOI MESFETs

A two-zone Green's function solution method is proposed to analytically model the potential distribution in the silicon film of fully depleted SOI MESFETs, in which the exact solution of 2-D Poisson's equation is obtained by using the appropriate boundary conditions. From the derived analytic 2-D potential distribution, the bottom potential in the active silicon film is used to analyze the drain-induced barrier lowering effect and the threshold voltage is defined in terms of minimum channel potential barrier. The results of the developed analytic threshold-voltage model are compared with those of 2-D numerical simulation, and good agreements are obtained for the gate length down to 0.1 μm with wide ranges of structure parameters and bias conditions     

A simplified 2-D analytic model for the threshold-voltage of fullydepleted short gate-length Si-SOI MESFET's

We present a simplified form of the exact solution of the 2-D Poisson equation of fully depleted Si-SOI MESFET's by Hou and Wu (1995). The major improvement is that the Fourier coefficient of the electric displacement at the Si-SiO₂ interface is given in (finite) closed form, rather than infinite series. Their 2-D analytic model for the threshold-voltage can be simplified accordingly     

小尺寸堆栈高k栅介质GaAs nMOSFET阈值电压模型

通过求解沟道的二维泊松方程,建立了小尺寸高k栅介质GaAs MOSFET的阈值电压模型．模型包括了短沟道效应、漏致势垒降低效应和量子效应．模拟结果与TCAD仿真结果符合较好,证实了模型的正确性和实用性．利用该模型,分析了堆栈高k栅介质结构及其物理参数对阈值电压漂移的影响以及阈值电压的温度特性．结果表明,堆栈栅介质结构能有效抑制边缘场和DIBL效应,改善MOSFET的阈值特性和温度特性;未考虑量子效应的模型过高估计了温度对阈值电压的影响。     

A compact double-gate MOSFET model comprising quantum-mechanicaland nonstatic effects

In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 μm. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort     

MOSFET simulation with quantum effects and nonlocal mobility model

We present a state-of-the-art two-dimensional (2-D) device simulator suitable for highly doped n-MOSFETs. Quantization effects in the inversion channel are accounted for by a self-consistent solution of the Poisson, current-continuity and Schrodinger equations. The electron charge is given by a density of electrons in the bounded levels plus a density of classically-distributed carriers. Consequently, different mobility models are used. For the former, we adopted a nonlocal, newly-developed mobility model, thus overcoming the deficiency of currently-used mobility models in the high-doping limit. We instead retained a standard local model for the classical regime. Results of the simulations are in good agreement with the experiments     

A long-channel MOSFET model

A MOSFET model valid for long-channel devices is derived. The model describes correctly the drain current and the small signal parameters in all regions of operation, including the subthreshold regime and the saturation regime. The model contains as an approximation the charge-sheet model proposed by Brews[1]. Mobility variations along the channel, resulting from the normal and lateral electric fields, can be taken into account.     

Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

A new threshold voltage (V/sub th/) model has been developed for the pocket-implant technology. The model extracts the threshold condition from the entire mobile charge concentration in the channel with only five additional parameters; the maximum doping concentration (N/sub subp/) of the pocket profile, the penetration length (L/sub p/) into the channel, and three enhanced short-channel parameters. The model reproduces the measured V/sub th/ versus. gate-length (L/sub gate/) characteristics with an average error of a few millivolts under any bias conditions.     

A nonquasi-static MOSFET model for SPICE-transient analysis

The long-channel MOSFET model is based on an approximate solution to the nonlinear current-continuity equation in the channel. The model includes the large-signal transient and the small-signal AC analyses, although only the transient model is reported here. Comparisons have been made between this model and the 1-D numerical solution to the current-continuity equation, 2-D device simulation (PISCES), and the quasistatic (QS) results. The channel-charge partitioning scheme in the charge-based QS models is shown to be inadequate for the fast transient. This model does not use a charge-partitioning scheme and the currents are dependent on the history of the terminal voltages, not just the instantaneous voltages and their derivatives. For the slow signals (compared to the channel transit time), the nonquasistatic (NQS) model is reduced to the quasistatic 40/60 channel-charge partitioning scheme. The CPU time required for this model is about two to three times longer than that of conventional MOSFET models in SPICE     

A precise MOSFET model for low-voltage circuits

A MOSFET model that is capable of handling the drain current above 10^-10A within the temperature range of 220-340 K is proposed. The key feature of the model is that surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions. Comparison of the model with experiments has been carried out using n-channel MOSFET's with 7 × 10¹³, 7 × 10¹⁴, and 4 × 10¹⁵cm^-3substrate impurity concentration and 675-, 1470-, and 5030-Å gate-oxide thickness. The theoretical calculations are in excellent agreement with the experimental measurements. It is shown that low-level current has a strong influence on the low-voltage static inverter circuit and dynamic memory.     

A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer

An analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson’s equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters.     

Inverse-narrow-width effects and small-geometry MOSFET thresholdvoltage model

An analytical threshold voltage model is developed based on the results from a three-dimensional MOSFET simulator, called MICROMOS. The model is derived by solving Poisson's equation analytically and is used to predict the threshold voltage of MOSFETs with fully recessed oxide isolation (the trench structure). Coupling was observed between the short-channel effect and the inverse-narrow-width effect. The coupling results from the mutual modulation of the depletion depth and is used to extend the analytical inverse narrow-width model to small-geometry devices. The model is compared with experimental data obtained from the literature as well as with the three-dimensional simulator. Satisfactory agreement for channel length down to 1.5 μm and channel widths down to 1 μm has been obtained     

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TND^-1Leff^-2, where T, ND, and Leffare the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.     

A new long-channel MOSFET model

A new highly accurate long-channel MOSFET model which is valid both in the linear and saturation regions by taking into account two-dimensional effects over the whole channel is presented in this paper. The calculated results are in excellent agreement with the experimental data. Compared with three other long-channel MOSFET models, the double integral model, the charge-sheet model and the single-integral model, our model has some advantages. The results demonstrate that two-dimensional effects are important in the current continuity near the drain end of the channel and cannot be neglected when the MOSFET is operating in saturation.     

A physical thermal noise model for SOI MOSFET

The recent progress in SOI technology necessitates an accurate thermal noise model for wide-band SOI analog IC design. In this paper a physical-based thermal noise model is proposed for floating-body SOI MOSFET operated in strong inversion regime and verified by the experimental data. In the model, both the lattice temperature (unique to SOI due to the buried oxide) and the carrier temperature (significant for short-channel device in saturation region) are considered. The model agrees well with the experimental data