Designing for recovery [software design]

How should you design your software to detect, react, and recover from exceptional conditions? If you follow Jim Shore's advice and design with a fail fast attitude, you won't expend any effort recovering from failures. Shore argues that a "patch up and proceed" strategy often obfuscates problems. Shore's simple design solution is to write code that checks for expected values upon entry and returns failure notifications when it can't fulfil its responsibilities. He argues that careful use of assertions allows for early and visible failure, so you can quickly identify and correct problems.     

Computing the Hough transform on a scan line array processor [imageprocessing]

A parallel algorithm for a line-finding Hough transform that runs on a linearly connected, SIMD (single-instruction, multiple-data-stream) vector of processors is described. The authors show that a high-precision transform, usually considered to be an expensive global operation, can be performed efficiently, in two to three times real time, with only local, communication on a long vector. The algorithm also illustrates a decomposition principle that has wide application in algorithm design for large linear arrays. A review of straight-line Hough transform implementations is also presented     

Designing an asynchronous processor using Petri nets

Using a simple example, we demonstrate how to design and analyze asynchronous systems from labeled Petri net specifications, later refining, transforming, and translating them for implementations     

Testing Gbps interfaces without a gigahertz tester

As device manufacturers scale their silicon technology, and processor speeds rise above 1 GHz, it's becoming common for every processor company to tout gigahertz processors. To continually improve system-level performance, system designers have begun increasing I/O performance. Some of these changes are evolutionary; some are revolutionary. The latter necessitate a change in test methodology and in the subsequent DFT. Intel's changing its processors' front-side bus from common-clock to source-synchronous (SS) signaling and increasing their bus transfer rate from less than 100 MHz to 800 megatransfers/second (1 MT/s= 1 Mbyte/s/pin). On the chipset side, Intel has upgraded its universal serial bus from 48 Mbps to 400 Mbps and has transitioned to the serial advanced technology attachment (SATA) standard at a 1.25-Gbps data rate. we show how we've solved the testing problem of the SS interface and how this self-test scheme is extendable to other high-speed I/O circuits, including high-speed serial (HSS) signaling.     

DBMS[me] [life-time records]

The article is concerned with time and the deluge of data that we can expect to collect and view. We examine this from the perspective of a subproblem, a database management system that records a person's life in its entirety - referred to here as DBMS[me] and E-me (that is, a database of me or an electronic model of me). Challenges for the DBMS[me] are to augment human memory by recording all data about an individual, to organize such data into models, and to develop security and privacy languages to control access to such models.     

一种用于浮点DSP的流水线结构DMA设计

本文提出了一种用于32位浮点DSP处理器的改进型DMA结构.采用两级数据流水线结构,外设与内部存储器的数据传输速率比原来提高了一倍.使用verilog HDL语言对其进行编码和仿真,仿真结果表明工作频率达到250MHz以上,满足设计要求.     

Non-negative integer basis algorithms for linear equations with integer coefficients

A new class of non-negative integer basis algorithms for linear equations with integer coefficients is developed. Computer experiments with one of the new algorithms and comparisons with other non-negative integer basis algorithms are reported. When the total run times for collections of common simple examples typical of automated deduction applications are computed, the new algorithm has been found to be significantly faster than previous algorithms.     

Making a case for BPC [Broadening Participation in Computing]

BPC program aims to significantly increase the number of students who are US citizens and permanent residents receiving postsecondary degrees in the computing disciplines. The BPC program seeks to engage the computing community in developing and implementing innovative methods to improve recruitment and retention of these students at the undergraduate and graduate levels. The NSF programs take a research approach to addressing the issues associated with broadening participation in computing. However there are few places where this type of research can be disseminated so that it would impact the computing community. This "Broadening Participation in Computing" series provides a forum for computer science researchers to present their findings and offer solutions that address these problems.     

[a,b]-缩减生成器

利用两个反馈移位寄存器（LFSR）构造了一类新型的缩减生成器——［a,b］-缩减生成器,证明了其输出序列的周期、线性复杂度、重量复杂度、k-错线性复杂度及其0、1个数。理论分析和局部随机性检验表明这类缩减生成器序列具有好的统计特性,适合流密码系统的使用。     

A shared matrix unit for a chip multi-core processor

This paper proposes extending a multi-core processor with a common matrix unit to maximize on-chip resource utilization and to leverage the advantages of the current multi-core revolution to improve the performance of data-parallel applications. Each core fetches scalar/vector/matrix instructions from its instruction cache. Scalar instructions continue the execution on the scalar datapath; however, vector/matrix instructions are issued by the decode stage to the shared matrix unit through the corresponding FIFO queue. Moreover, scalar results from reduction vector/matrix instructions are sent back from the matrix unit to the scalar core that sent these instructions. Some dense linear algebra kernels (scalar–vector multiplication, scalar times vector plus another, apply Givens rotation, rank-1 update, vector–matrix multiplication, and matrix–matrix multiplication) as well as discrete cosine transform, sum of absolute differences, and affine transformation are used in the performance evaluation. Our results show that the improvement in the utilization of the shared matrix unit with a dual-core ranges from 9% to 26% compared to extending a matrix unit to a single-core. Moreover, the average speedup of the dual-core shared matrix unit over a single-core extended with a matrix unit ranges from 6% to 24% and the maximum speedup ranges from 13% to 46%.     

An analog processor architecture for a neural network classifier

Many neural-like algorithms currently under study support classification tasks. Several of these algorithms base their functionality on LVQ-like procedures to find locations of centroids in the data space, and on kernel (or radial-basis) functions centered on these centroids to approximate functions or probability densities. A generic analog chip could implement in a parallel way all basic functions found in these algorithms, permitting construction of a fast, portable classification system     

SNEE: a query processor for wireless sensor networks

A wireless sensor network (WSN) can be construed as an intelligent, large-scale device for observing and measuring properties of the physical world. In recent years, the database research community has championed the view that if we construe a WSN as a database (i.e., if a significant aspect of its intelligent behavior is that it can execute declaratively-expressed queries), then one can achieve a significant reduction in the cost of engineering the software that implements a data collection program for the WSN while still achieving, through query optimization, very favorable cost:benefit ratios. This paper describes a query processing framework for WSNs that meets many desiderata associated with the view of WSN as databases. The framework is presented in the form of compiler/optimizer, called SNEE, for a continuous declarative query language over sensed data streams, called SNEEql. SNEEql can be shown to meet the expressiveness requirements of a large class of applications. SNEE can be shown to generate effective and efficient query evaluation plans. More specifically, the paper describes the following contributions: (1) a user-level syntax and physical algebra for SNEEql, an expressive continuous query language over WSNs; (2) example concrete algorithms for physical algebraic operators defined in such a way that the task of deriving memory, time and energy analytical cost-estimation models (CEMs) for them becomes straightforward by reduction to a structural traversal of the pseudocode; (3) CEMs for the concrete algorithms alluded to; (4) an architecture for the optimization of SNEEql queries, called SNEE, building on well-established distributed query processing components where possible, but making enhancements or refinements where necessary to accommodate the WSN context; (5) algorithms that instantiate the components in the SNEE architecture, thereby supporting integrated query planning that includes routing, placement and timing; and (6) an empirical performance evaluation of the resulting framework.     

The 3DP: a processor architecture for three-dimensionalapplications

The 3DP (3-Dimensional Processor), a parallel-computing architecture that targets problems that have a 3-D numerical structure and require numerous calculations on 3-D vectors, is described. The 3DP architecture differs from traditional scalar architectures in that it operates directly on vectors. It differs from general parallel architectures in that it can solve problems that predict the behavior of highly coupled systems, and it differs from vector architectures in that it runs efficiently on length-3 vectors. Object-oriented programming on the 3DP and programming the 3DP in C++ are discussed. 3DP performance is reviewed, and the current implementation of the 3DP architecture, as an attached processor that plugs directly into Sun host VMEbus, is described