CMOS图像传感器的研究进展

20世纪90年代以来,随着超大规模集成(VLSI)技术的发展,CMOS图像传感器显示出强劲的发展势头.简要介绍了CMOS图像传感器的结构及工作原理,详细比较了CMOS图像传感器与CCD的性能特点,讨论了CMOS图像传感器的关键技术问题.并给出了相应的解决途径,综述了GMOS图像传感器的国内外研究现状,最后对CMOS图像传感器的发展趋势进行了展望.     

CMOS图像传感器的研究新进展

随着超大规模集成技术的发展,CMOS图像传感器显示出了强劲的发展趋势.简要介绍了CMOS图像传感器的发展历程,在分析CCD和CMOS图像传感器工作原理的基础上,对比了CMOS图像传感器与CCD的特点.重点描述了国外CMOS图像传感器的最新商业化产品状况,同时给出了一些产品的性能参数,最后展望了CMOS图像传感器的未来发展趋势.     

CMOS图像传感器的发展及应用

比较了CMOS图像传感器与CCD图像传感器的优缺点，分析了CMOS图像传感器的结构、研制现状、应用及市场前景。指出随着CMOS传感器技术的发展，CMOS图像传感器可以代替CCD图像传感器，并预见了其发展趋势。     

CMOS图像传感器及其发展趋势

本文简要介绍了CMOS图像传感器的发展历程及工作原理.对CCD图像传感器与CMOS图像传感器的优缺点进行了比较,指出了CMOS图像传感器的技术优势,并讨论了CMOS图像传感器的发展趋势.     

CMOS图像传感器赶超CCD图像传感器

比较了CMOS图像传感器与CCD图像传感器的优缺点，分析了CMOS图像传感器的结构、研制现状、应用及市场前景。提出了随着CMOS图像传感器技术的发展，CMOS图像传感器可以代替CCD图像传感器，并对其发展趋势作了预见。     

传感器

采用增强型像素结构的CMOS图像传感器;可用在极恶劣环境下的不锈钢视觉传感器;全集成200万像素CMOS图像传感器.     

CMOS图像传感器及其研究

介绍了CMOS图像传感器的工作原理,比较了CCD图像传感器与CMOS图像传感器的优缺点,指出了CMOS图像传感器的技术问题和解决途径,综述了CMOS图像传感器的现状和发展趋势.     

CMOS图像传感器研究

结合CMOS图像传感感器的研究背景,从5个方面对CMOS图像传感器与CCD图像传感器的优缺点进行了比较,重点分析了CMOS图像传感器的结构、工作原理以及影响传感器性能的主要因素,并给出了相应的解决方法。最后,预测CMOS图像传感器的技术发展趋势。     

CMOS APS 器件及其在星敏感器中的应用

介绍了CMOS有源像元图像传感器(APS)的原理与结构特点,阐述了CMOS APS与CCD比较应用于星敏感器的潜在优势,详细介绍了CMOS图像传感器在星敏感器中的应用现状,并对基于CMOS APS与基于CCD的星敏感器的测量精度结果进行对比,展望了CMOS APS星敏感器的发展前景.     

CMOS图像传感器在视频监控系统中的应用

介绍了CMOS图像传感器的工作原理、总体结构,并具体介绍了一种CMOS图像传感器MT9M001的内部结构、特点及应用.在此基础上给出了CMOS图像传感器MT9M001在视频监控系统中的具体应用实例.该设计在低成本的条件下具有图像质量好、图像分辨率高等显著特点,具有较宽的应用范围和较高的研究价值.     

Fracture Mechanics of Solder Bumps During Ball Shear Testing: Effect of Bump Size

This paper examines the mechanics of ball shear testing with the objective of understanding the mechanism by which the maximum shear force and the rate of crack growth is dependent on the solder bump size. For this, Pb-Sn solder bumps with diameters between 460 μm and 760 μm are soldered to 400 μm-diameter Cu pads and subjected to ball shear testing. In spite of the constant interface area, the bump size significantly impacts the measured shear fracture force and the crack growth rate. Both the fracture force and the crack growth rate increase with bump size, and in the case of the fracture force, the increase is almost linear. Our analysis finds that the linear increase in the fracture force is a result of the bump deformation force, which increases with bump size. A simple model that accounts for the deformation force component is developed and used to extract the true interface fracture force. The estimated true interface fracture force is found to vary little with bump size, tightly converging to the 40 MPa to 48 MPa range. On the other hand, the dependence of crack growth rate on bump size is found to result from the higher degree of rotational moment associated with larger bumps.     

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件—智能像素面阵 ,对倒装焊的工艺过程作了简要的介绍。该面阵采用铟做凸点材料 ,制作了输入输出数达 6 4× 6 4的凸点电极阵列 ,并采用回流焊的方式 ,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接 ,形成输入输出引线间距只有 80 μm的面阵器件     

The microstructure characterization of ultrasmall eutectic Bi-Sn solder bumps on Au/Cu/Ti and Au/Ni/Ti under-bump metallization

The microstructure of the ultrasmall eutectic Bi-Sn solder bumps on Au/Cu/Ti and Au/Ni/Ti under-bump metallizations (UBMs) was investigated as a function of cooling rate. The ultrasmall eutectic Bi-Sn solder bump, about 50 μm in diameter, was fabricated by using the lift-off method and reflowed at various cooling rates using the rapid thermal annealing system. The microstructure of the solder bump was observed using a backscattered electron (BSE) image and the intermetallic compound was identified using energy dispersive spectroscopy (EDS) and an x-ray diffractometer (XRD). The Bi facet was found at the surface of the ultrasmall Bi-Sn solder bumps on the Au/Cu/Ti UBM in almost all specimens, and the interior microstructure of the bumps was changed with the solidification rate. The faceted and polygonal intermetallic compound was found in the case of the Bi-Sn solder bump on the Au (0.1 μm)/Ni/Ti UBM, and it was confirmed to be the (Au_1−x−yBi_xNi_y)Sn₂ phase by XRD. The intermetallic compounds grown form the Au (0.1 μm)/Ni/Ti UBM interface, and they interrupted the growth of Bi and Sn phases throughout the solder bump. The ultrasmall eutectic Bi-Sn solder bumps on the Au (0.025 μm)/Ni/Ti UBM showed similar microstructures to those on the Au/Cu/Ti UBM.     

Characterization of small-sized eutectic Sn-Bi solder bumps fabricated using electroplating

We studied the effects of the cooling rate during the reflow process on the microstructure of eutectic Sn-Bi solder bumps of various sizes fabricated by electroplating. To fabricate eutectic Sn-Bi solder bumps of less than 50 μm in diameter, Sn-Bi alloys were electroplated on Cu pads and reflowed at various cooling rates using the rapid thermal annealing system. The interior microstructure of electroplated bumps showed a fine mixture of Sn-rich phases and Bi-rich phases regardless of the cooling rate. Such an interior microstructure of electroplated bumps was quite different from the reported microstructure of vacuum-evaporated bumps. Ball shear tests were performed to study the effects of the cooling rate on the shear strength of the solder bumps and showed that the shear strength of the bumps increased with increasing cooling rate probably due to the reduced grain size. Soft fractures inside the solder bump were observed during the ball shear test regardless of the cooling rate.     

Defect inspection of solder bumps using the scanning acoustic microscopy and fuzzy SVM algorithm

Flip chip technology has been extensively used in high density electronic packaging over the past decades. With the decrease of solder bumps in dimension and pitch, defect inspection of solder bumps becomes more and more challenging. In this paper, an intelligent diagnosis system using the scanning acoustic microscopy (SAM) is investigated, and the fuzzy support vector machine (F-SVM) algorithm is developed for solder bump recognition. In the F-SVM algorithm, we apply a fuzzy membership to input feature data so that the different input features can make different contributions to the learning procedure of the network. It solves the problem of feature data aliasing in the traditional SVM. The SAM image of flip chip is captured by using an ultrasonic transducer of 230 MHz. Then the segmentation of solder bumps is based on the gradient matrix of the original image, and the statistical features corresponding to every solder bump are extracted and adopted to the F-SVM network for solder bump classification and recognition. The experiment results show a high accuracy of solder defect recognition, therefore, the diagnosis system using the F-SVM algorithm is effective and feasible for solder bump defect inspection.     

FCBGA高铅凸块non-wet的失效机制及基于封装工艺的解决方案

FCBGA封装芯片中晶片凸块和基片凸块之间的non-wet问题是一个已知的能导致严重低良品率和引入可靠性隐患的问题。本文研究了FCBGA封装形式中non-wet的典型失效模式和揭示了其生成机制, 并确定了晶片凸块表面残留的铅和锡氧化物是导致晶片凸块和基片凸块之间non-wet的主要成因。晶片凸块回流工艺实验表明,优化后的回流时间和氢气流速能显著减少和去除晶片凸块表面的铅锡氧化物,从而能把non-wet引起的报废率降低90%左右。 失效分析结果和量产数据都验证了本文揭示的non-wet的失效机制是正确的。 研究确定的凸块回流工艺的优化参数显著降低了non-wet引起的报废率,从而大大地节省了制造成本和提高了产能利用率。     

10 μm间距红外探测器铟柱制备研究

小间距红外探测器目前已成为红外探测器技术发展的一个重要方向.用于连接探测器芯片与读出电路芯片的铟柱的制备工艺水平成为影响器件性能的一个重要因素.介绍了一种10μm间距红外探测器铟柱的制备工艺.新工艺采用多次铟柱生长结合离子刻蚀的手段,最终剥离和制备出高度为8 μm、非均匀性小于5％的10μm间距红外探测器读出电路铟柱,...     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.     

Golden bump for 20 micron diameter wire bond enhancement at reduced process temperature

With the rapid development of advanced microelectronic packaging technologies, research on fine-pitch wire bonding with improved reliability is driven by demands for smaller form factors and higher performance. In this study, thermosonic wire bonding process with a 20 μm wire for fine-pitch interconnection is described. To strengthen stitch bonds made in a gold-silver bonding system when the bonding temperature is as low as 150 °C, ball bumps (security bump) are placed on top of the stitch bonds. The ball-stitch bond and bump forming parameters are optimized using a design of experiment (DOE) method. A comparison of pull test results for stitch bonds with and without security bumps shows a substantial increase of the stitch pull force (PF) due to the use of security bonds. By varying the relative position of the security bumps to the stitch bonds via wedge shift offset (WSO), a WSO window ranging from 15 to 27 μm results in stitch PF higher than 7 gf, which is equivalent to an increase in average stitch PF of 118%.