Quantum flux type logic circuits utilizing Josephson junctiontransmission lines

A quantum-flux-type logic circuit is proposed which is composed of Josephson junction transmission lines, along which localized magnetic flux can propagate. By choosing bias current properly, the duplication of magnetic flux and a variety of logical functions can be obtained without changing the circuit topology. Computer simulation results are presented on AND and OR operations with two and three inputs for the same circuit topology, confirming that these circuits can be used as logic circuits. The simulations demonstrate the high-speed operation and low power consumption of this circuit     

Josephson shift register design and layout

Integrated circuit chips were designed and fabricated, based on a Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25-mm² chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO_x/Nb Josephson junctions with a design value of 2000 A/cm² critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. A layout geometry for the superconductive transmission lines and thin-film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2° at 10 GHz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers     

An integration of all refractory Josephson logic LSI circuit

An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.     

A Josephson ternary associative memory cell

The authors describe a three-valued content-addressable memory cell using a Josephson complementary ternary logic (JCTL) circuit. The memory cell can perform the operations of searching, writing and reading in the ternary logic system. The principle of the memory circuit is illustrated in detail by using the threshold characteristics of the JCTL. Computer simulations were performed to investigate how high-performance operation can be achieved. Simulation results show that the cycle time of memory operation is 120 ps, power consumption is about 0.5 μW/cell, and tolerances of writing and reading operation are ±15% and ±24% respectively     

Logic devices based on inductive Josephson logics

Inductive Josephson logic (IJL) is realized by using Josephson junctions as a kind of nonlinear inductance. The operational principle of inductive Josephson logic is studied from a very simple example and generalized to multiple Josephson inductive logic devices. Concepts offorward andbackward are introduced to describe the states of the operations. IJLs operate in terms of current or flux; they are suitable to be used in connection with other flux-control Josephson circuit devices such as DC SQUID or DCFP. Some circuit devices based on the principle of inductive Josephson logic are given as examples of IJL logic functions.     

A Novel High-Speed Multiplexing IC Based on Resonant Tunneling Diodes

A new multiplexing IC based on the resonant tunneling diode (RTD) is proposed. The unique negative differential resistance characteristics arising from quantum effects of the RTD enable us to develop a new functional low-power digital circuit. The proposed multiplexing IC consists of two current-mode-logic monostable-bistable transition logic elements (CML-MOBILEs) based on the RTD and a low-power selector circuit block. The proposed circuit has been fabricated by using an InP RTD/ heterojunction bipolar transistor monolithic microwave integrated circuit technology. The multiplexing operation of the fabricated quantum effect IC has been confirmed up to 45 Gb/s for the first time as a monolithic technology based on the quantum effect devices. The dc power consumption is only 23 mW, which is found to be one-fourth of the current state-of-the-art conventional transistor-based multiplexing IC.     

A novel ternary logic circuit using Josephson junction

A novel Josephson complementary ternary logic (JCTL) circuit is described. This fundamental circuit is based on the combination of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT, and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. Simulation results show that reliable operation of these circuits can be achieved with a high performance     

An all-NbN time domain reflectometer chip functional above 8 K

Niobium nitride has a superconducting transition temperature nearly twice that of niobium. A 5-ps time-domain reflectometer chip based on NbN technology has been designed, fabricated, and tested. The circuit is operable up to 9 K. The NbN process and limitations are discussed, and present drawbacks in the junction fabrication method are pointed out. Electrical properties are discussed, the circuit operation is described, and simulations are presented that are based on model parameters extracted from device measurements. The actual output of the circuit is presented as evidence of basic functionality. This is the first demonstration of a functional high-speed circuit based entirely on a compound superconductor technology and operable at temperatures above 8 K     

First Direct Comparison of a Cryocooler-Based Josephson Voltage Standard System at 10 V

A commercially available and fully automated 10-V Josephson voltage standard system with a liquid helium free cooling has been developed as a result of the cooperation between the Institute of Photonic Technology and Supracon AG, both in Jena, Germany. The system operates with an array of 19 700 superconductor–insulator–superconductor Josephson tunnel junctions installed in a pulse tube cooler. A stable operation is achieved by the proper integration of the voltage standard circuit to the cold stage of the cryocooler. Different operation setups are discussed. A direct comparison of a cryocooler-based Josephson voltage standard system versus a liquid-helium-based system was performed at a voltage level of 10 V. We obtained a voltage difference of 1.3 nV with a total combined uncertainty of 2 nV. This corresponds to a relative uncertainty of $2 times 10^{-10}$.      

Josephson semiconductor interface circuit

This paper describes an output interface circuit which allows Josephson circuits to communicate with semiconductor circuits. The circuit combines Josephson and GaAs drivers to drive a 50 μ load at a signal level of semiconductor circuits. The output voltage of 2.8 mV (usual for Josephson gates using Nb/AlO_x/Nb junctions) was increased to 1.7 V. The interface circuit has been operated up to 800 MHz.     

Comparison of a Multichip 10-V Programmable Josephson Voltage Standard System With a Superconductor–Insulator–Superconductor-Based Conventional System

We developed a 10-V dc programmable Josephson voltage standard (PJVS) using a multichip technique. The PJVS was based on $hbox{NbN/TiN}_{x}/hbox{NbN}$ junctions and operated using a 10-K compact cryocooler. We carried out an indirect comparison with a superconductor–insulator–superconductor-based conventional Josephson voltage standard (JVS) by measuring the voltage of a 10-V zener diode reference standard. The combined standard uncertainty of the comparison was $u_{c} = 0.03 muhbox{V}(k = 1)$, and the relative combined standard uncertainty was $3 times 10^{-9}$.      

A Josephson logic design employing current-switched junctions

A logic scheme using Josephson tunnel junctions in a current-steering mode is described. Switching from voltageV = 0toV neq 0is accomplished by adding a fraction of the control-line currents to the bias current. In one form the addition is accomplished by shunting the junction to be switched with a loop containing a second junction serving a diode-like function and causing one or more control lines to possess inductive coupling to the loop. A five-element circuit demonstrating AND, OR and INVERSION operations carried out by this approach has been fabricated and works as expected.     

Surface impedance of NbN superconducting thin films by Josephson measurements

The microwave quality factorQ of NbN-Pb Josephson junctions has been determined via measurements of the amplitude of Fiske resonant modes in the junctions at different resonant frequencies in the range 30–300 GHz. It is proved that, for our samples, the main contribution to theQ comes from the surface impedance of the filmsR _s . Data show that, for NbN,R _s v^1.5±0.1 atT _c =4.2 K in the frequency range considered. The implications of our results for the possible applications of NbN films both in the context of Josephson microwave devices and as a coating material for rf cavities in high-energy physics are discussed.     

Controlling Chaos in the RF-Biased Josephson Junction with Thermal Noise

In this paper the control of chaos in the rf-biased Josephson junction circuit is studied. Numerical simulation indicates that the unstable periodic orbits (UPO) embedded in the chaotic attractor can be stabilized with the delayed feedback technique. Upon controlling, operation state of the chaotic Josephson junction circuit switches back to its conventional state. Namely, phase locking is reestablished and typical I-V curve recovers. Furthermore, we investigate the influence of thermal noise on the control and estimate the range of the environmental temperature for an effective control through numerical simulation.     

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 μW/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself     

35000m~3/h空分设备分子筛纯化系统逻辑控制及优化

简介鞍钢股份有限公司氧气厂3#35000 m3/h空分设备分子筛纯化系统结构和工艺流程,介绍分子筛纯化系统阀门自动开关控制逻辑、顺控程序自动/手动运行、顺控程序执行过程,以及根据现场生产运行实际情况,对分子筛吸附器顺控组态程序进行的优化改进。     

Josephson quantum interference computer devices

Josephson devices are potential elements for ultra-fast computers. Rather complex logic and memory circuits have been realized. Here quantum interference devices with improved speed and power performance are discussed. Latching and non-latching logic operation is possible and experiments with non-latching circuits are reviewed. Memory applications of quantum interference devices are also considered.     

Direct-coupled high speed adder by using Josephson junction

This paper presents the latest design work of high speed adder logic based on Josephson elements. The Josephson adder uses a novel exclusive-OR logic and performs high speed carry propagation technique. The idea of directionality is also undertaken to avoid the necessary distortion in carry signal. The principle of operation with salient feature of simulation of the adder are presented in full detail. Necessary checks for carry skip and other fabrication parameters are investigated using detailed model of the device based on its highly miniaturized size. The results of the simulation show that the nominal delay of the adder logic is 20 ps/stage and average power dissipation is 47 μW/stage. Authors have mainly stressed upon how to obtain ultra fast speed at the cost of very low power dissipation of the presented adder with its small size.     

Carbon-nanotube-based voltage-mode multiple-valued logic design

Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a/spl grave/-vis traditional complementary field-effect transistor binary logic family has been presented.     

Chaotic Dynamics of Externally Shunted Josephson Junction with Unharmonic CPR

The current–phase relation (CPR) of Josephson junctions based on high-T _c superconductors and other types of superconducting structures contain second harmonics. In this work, the influence of second harmonics of CPR on an externally shunted Josephson junction circuit model with nonzero inductance has been studied to analyze the chaotic dynamics of the system. Having constructed the circuit model, the time dependent simulations are carried out for a variety of control parameters. It is shown that the presence of second harmonics leads to a change in the boundary of the chaotic region in bifurcation diagram.