4096-bit serial decoded multiphase serial-parallel-serial CCD memory

A new practical form of charged-coupled device (CCD) memory structure is described which achieves high storage density while providing low clock-line capacitance. In the new structure, the time-division multiplexing of multiphase concepts is replaced by the spatial multiplexing of a serial-parallel-serial (SPS) array. By using a ring counter to generate the multiphase clocking, a compact method of clock generation is described which allows the integration of multiphase drivers into the memory array. The improved density results from using a multiphase technique while the low clock-line capacitance stems from integrating the necessary drivers into the memory structure. The average bit density of the new structure including all necessary drivers exceeds that of previously discussed CCD memory structures when similar layout rules and gate electrode configurations are applied.     

A 16-kbit block addressed charge-coupled memory device

This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

A 16 384-bit high-density CCD memory

A 16 384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45 × 4.29 mm²(136 × 169 mil²), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 µW/bit.     

A 16-kbit Block Addressed Charge-Coupled Memory Device

This paper describes the design and performance of a 16-kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 /spl mu/W/bit with another 0.5 /spl mu/W/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil²and the total chip size is 218 × 235 mil². The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.     

The behavior of the continuously charge-coupled random-access memory (C/SUP 3/RAM)

This paper describes a new random-access memory which achieves a bit density comparable to CCD memories. This memory uses as storage elements single-transistor memory cells which are connected to a common bit line. The bit line is implemented with an MOS transmission line, which makes possible an almost lossless charge transport from the single-transistor memory cell to the read/write amplifier. Due to the almost lossless charge transport, the storage capacitance can be reduced and the bit density increased. The expected performance of a 32-kbit memory has been derived.     

A surface-charge random-access memory system

The authors present a surface-charge storage cell suitable for word-organized dynamic random-access memory and discuss its operation in a memory system. Experimental results and computer simulations of the readout process on a 4/spl times/8 array using this cell are given. A sensitive stable sense-and-refresh amplifier, suitable for use with this memory cell is also described. Simulations of a 4096-bit chip with a storage cell density of 2.5 mils/SUP 2//bit using this refresh amplifier predict a cycle time of 250 ns.     

A 16384-bit high-density CCD memory

A 16384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45/spl times/4.29 mm/SUP 2/ (136/spl times/169 mil/SUP 2/), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 /spl mu/W/bit.     

A new multiplexed electrode-per-bit structure for a 64-kbit charge-coupled-device memory

An advanced form of the multiplexed electrode-per-bit (ME/B) structure is described for CCD memory applications. In the new structure, a merging serial register is combined with an ME/B array to make a practical and flexible CCD array. The resulting structure is called the merging ME/B (M/SUP 2/E/B). An n-channel two-level polysilicon-gate structure with ion-implanted barriers and offset CCD clocks lead to a simple rectangular layout, in addition to low power consumption. A 64-kbit CCD memory utilising the structure was designed and tested. The memory operates typically at 5-Mbits/s data rate, while a 512-bit test array is operated in less than 140-ns transfer execution time.     

CCD memory using multilevel storage

In CCD multilevel storage, more than one bit of information is stored in a charge packet. Requirements for CCD MLS systems are described, and circuits for the encoding and decoding of charge packets which operate essentially independent of device parameter and geometric tolerances are presented. 3-bit operation on a short shift register loop is demonstrated. Requirements on leakage and transfer in efficiency for 2- and 3-bit MLS are discussed.     

Design of a 16384-bit serial charge-coupled memory device

This paper describes a 16384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil/SUP 2//bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 /spl mu/s.     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

Dynamic CMOS amplifiers

The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.     

Design of a 16 384-bit serial charge-coupled memory device

This paper describes a 16 384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil²/bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 µs.     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

8路光纤水听器高速时分复用系统设计

当前,光纤水听器阵列的多路复用技术已成为研究的重要课题之一,而时分复用(TDM)技术被认为是最简单有效的方案。本文详细介绍了8路光纤水听器高速时分复用系统的设计过程。分析比较了梯形式及平行式两种光路结构的优缺点,并得出最佳光路方案。选择TI公司生产的TMS320F206芯片作为系统控制核心,采用AD公司新出的采样频率达1 M的16位AD7677作为A/D转换器,设计出8路光纤水听器高速时分复用系统,测试结果表明系统通道间串扰在-30 dB左右。对水听器阵列时分复用技术的发展具有相当的参考价值和借鉴意义。     

An 8-kbit content-addressable and reentrant memory

A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size associative memory cell (30/spl times/36 /spl mu/m/SUP 2/) with 2-/spl mu/m CMOS technology, while a double-layer metallization technique, new circuits for the control-signal propagation, and a hierarchical structure for the address encoder of the chip allow fast access. This device has reentrant mode operation, where the on-chip garbage collection or data storage is accomplished conditionally. One of the practical applications of this device, a high-speed matching unit for dataflow computers, is also discussed.     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.