Wafer emissivity independent temperature measurements

A study on the techniques to yield wafer emissivity independent temperature measurements in rapid thermal processing has been presented. This study focuses on the Steag-AST Electronik approach to enhance wafer emissivity by using the Hotliner*. The Hotliner comprises of a heavily doped p-Si substrate sandwiched with Si₃N₄/SiO₂ from both sides. Experimental measurements on the optical properties of the Hotliner using a spectral emissometer operating in the wavelength range of 1–20 μm are presented here. Results of the simulation of the experimental data using the MIT/SEMATECH Multi-Rad model are discussed. Hotliner is a trademark of Steag-AST Electronik, patent pending.     

Scanning spreading resistance microscopy of defect engineered low dose SIMOX samples

Modification of SiO₂ precipitate formation by defect engineering of SIMOX (separation by implanted oxygen) process was studied using cross section scanning spreading resistance microscopy (SSRM). Firstly, open volume defects, nanocavities, have been introduced by He⁺ ion implantation in the region, where SiO₂ precipitates were subsequently formed. Secondly, dual (simultaneous) oxygen (O⁺) and silicon (Si⁺) implantation was used to modify SiO₂ reaction kinetics too. The results show that the He-induced nanocavities enhance the SiO₂ formation presumably releasing excess strain associated with Si oxidation, while the use of a dual O⁺/Si⁺ beam do not influence significantly the oxidation kinetics in the initial state of the SIMOX process in our samples. Overall, SSRM was shown to be a suitable method for observation of the early stage of buried oxide formation in Si, since it measures the local resistivity, the main functional parameter of a SIMOX structure.     

Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

The Substrate Effects on Kinetics and Mechanism of Solid-Phase Crystallization of Amorphous Silicon Thin Films

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using Si₂H₆ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer (SiO₂/Si), quartz and LPCVD-oxide, and annealed at 600 °C in an N₂ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the SiO₂/Si starts from the interface between the a-Si and the substrate, so called interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.     

Growth and characterization of silicon oxide films formed in the presence of Si,SiC, and Si3N4

In order to comparatively study the growth and characterization of silicon oxide films on Si-based substrates, top-cut solar grade silicon (SOG-Si) containing Si₃N₄ rods and SiC lumps were used as raw materials and respectively heated at 1773 K and 1873 K under Ar gas. The samples were investigated by Focus Ion Beam/Scanning Electron Microscope (FIB/SEM) and Energy Dispersive Spectroscopy (EDS). Results indicated that silicon oxides with different morphologies successfully grew on the substrates via various mechanisms. Passive oxidation was evident in the formation of a dense SiO₂ surface layer on the base material at 1773 K, while active oxidation was evident in the formation of SiO₂ with particle, rod, and nanowire-like morphologies, which was the re-oxidation product of SiO at 1873 K under the active-to-passive transition. Si, SiC, and Si₃N₄ have the similar oxidation tendency to form silicon oxides under either passive or active regimes.     

The effect of low pressure chemical vapor deposition of silicon nitride on the electronic interface properties of oxidized silicon wafers

The effect of LPCVD Si₃N₄ film deposition on oxidized Si wafers, to form Si₃N₄/SiO₂/Si stacks, is studied using capacitance–voltage and carrier lifetime measurements. The deposition of a nitride film leads to an increase in the density of defects at the Si–SiO₂ interface, with the increase being greater the thinner the oxide. However, even the presence of a very thin intermediate oxide results in a dramatic improvement in interface properties compared to the direct deposition of the Si₃N₄ film on Si. The interface degradation occurs in the initial stages of nitride film deposition and appears to be largely the result of increased interfacial stress. Subsequent thermal treatments do not result in significant further degradation of the Si–SiO₂ interface (except for a loss of hydrogen), again in contrast to the case where the nitride films is deposited onto Si. Copyright © 2007 John Wiley & Sons, Ltd.     

Improved nanocrystal formation,quantum confinement and carrier transport properties of doped Si quantum dot superlattices for third generation photovoltaics

An all‐Si tandem solar cell has the potential to achieve high conversion efficiency at low cost. However, the selection and synthesis of candidate material remain challenging. In this work, we show that the conventional ‘Si quantum dots (Si QDs) in SiO₂ matrix’ approach can lead to the formation of over‐sized Si nanocrystals especially when doped with phosphorous, making the size‐dependent quantum confinement less effective. Also, our investigation has shown that the high resistivity of this material has become the performance bottleneck of the solar cell. To resolve these matters, we propose a new design based on Si QDs embedded in a SiO₂/Si₃N₄ hybrid matrix. By replacing the SiO₂ tunnel barriers by the Si₃N₄ layers, the new material manages to constrain the growth of doped Si QDs effectively and enhances the apparent band gap, as shown in X‐ray diffraction, Raman, photoluminescence and optical spectroscopic measurements. Besides, electrical characterisation on Si QD/c‐Si heterointerface test structures indicates the new material possesses improved vertical carrier transport properties. Copyright © 2011 John Wiley & Sons, Ltd.     

Water-enhanced negative bias temperature instability in p-type low temperature polycrystalline silicon thin film transistors

Water-enhanced degradation of p-type low temperature polycrystalline silicon thin film transistors under negative bias temperature (NBT) condition is studied. H₂O penetration into gate oxide network and the role of H₂O during NBT stress are confirmed and clarified respectively. To prevent H₂O diffusion, a combination of a layer of PECVD SiO₂ and a layer of PECVD Si₃N₄ as passivation layers are investigated, revealing that 100 nm SiO₂ and 300 nm Si₃N₄ can effectively block H₂O diffusion and improve device NBT reliability.     

Single and Multiple‐Step Dip‐Coating of Colloidal Maghemite (γ‐Fe2O3) Nanoparticles onto Si,Si3N4, and SiO2 Substrates

The adsorption behavior of colloidal maghemite (γ‐Fe₂O₃) nanoparticles, passivated by oleic acid and dispersed in octane solution, onto three different substrates (Si, Si₃N₄, and SiO₂) is investigated. The average nanoparticle size is 10 nm, with a size variation (σ) less than 5 %. The adsorption of particles is strongly dependent on both the type of substrate and the particle concentration in solution. By a single‐dipping process, we have obtained a maximum coverage of 0.45 on a Si substrate, but much less on other substrates (0.19 on Si₃N₄ and 0.14 on SiO₂). The particle coverage was drastically increased by the multiple‐adsorption process, where the process of dipping and drying was repeated multiple times. With this process, we can obtain a maximum particle coverage of about 0.76 on a Si substrate and 0.61 on a thermally grown SiO₂ substrate.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

Reliability of charge trapping memories with high-k control dielectrics (Invited Paper)

In this paper, we evaluate the potentiality of high-k materials (Al₂O₃, HfO₂ and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO₂/Si₃N₄/SiO₂/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention.     

Simulation of electronic structure of Si–Si bond traps in oxide/nitride/oxide structure

Numerical simulation using MINDO/3 was performed to study the electronic structure of Si–Si bond traps in the silicon oxide/nitride/oxide structure. Results show that the neutral diamagnetic Si–Si bond in Si₃N₄ can capture both electrons and holes. Simulation results also suggest that the creation of charged diamagnetic defect pairs is unfavorable in Si₃N₄. Electron and hole trapping models are also proposed for the Si–Si bond.     

Breakdown properties of metal/NIDOS SiO2/silicon structures

NIDOS/SiO₂/silicon structures have been annealed in a nitrogen (N₂) ambient and X-ray photoelectron spectroscopy (XPS) characterization has been performed in order to definitively demonstrate the nitrogen atoms out-diffusion from the nitrogen doped silicon (NIDOS) film towards the buried oxide layer. The nitridation of the SiO₂ layer is related to the competition between nitrogen atoms out-diffusion phenomena on one side into the underlying oxide layer and on the other side into an oxynitride layer grown during annealing. In order to analyse and optimize the corresponding MIS process, different structures such as metal/SiO₂/silicon, metal/(NH₃-‘nitrided’)SiO₂/silicon, metal/(N₂O-nitrided)SiO₂/silicon, metal/poly-Si*/SiO₂/silicon (* indicates deposited from disilane Si₂H₆) and metal/NIDOS/SiO₂/silicon have been realized and compared by capacitance–voltage, current–voltage and ageing under constant current injection experiments. The optimization of the NIDOS-nitridation process gives the highest charge-to-breakdown for the lowest nitridation level or even for no intentional nitridation. The dielectric breakdown improvement should therefore not be related to the nitridation phenomena alone but also to the intrinsic properties of the polysilicon layer itself.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

Fully coherent Ge islands growth on Si nano-pillars by selective epitaxy

Our recent experimental results of Ge nanoheteroepitaxy (NHE) on Si nanopillars (NPs) are reviewed to confirm the possibility of relaxed Ge growth on Si without misfit dislocations (MDs) formation by elastic deformation. Selective Ge growth is performed by using reduced pressure chemical vapor deposition (CVD) on two types of Si NPs with thermal SiO₂ or CVD SiO₂ sidewalls and on Si nanoislands (NIs) on SiO₂. By using thermal SiO₂ sidewall, compressive strain is generated in the Si pillar and fixed by the thermal SiO₂. This results in an incoherent Ge growth on Si NPs due to MD formation. By using CVD SiO₂ sidewall, tensile strain formation due to thermal expansion during prebake for Ge epi process is observed. However, strain in Si due to Ge growth is not dominant. By introducing a Si_0.5Ge_0.5 buffer layer, no MD and stacking faults are observed by cross section TEM. The shape of Ge on Si NPs becomes more uniform due to improved crystal quality. On Si NIs on SiO₂, a clear compliance effect is observed after Ge growth. Coherent growth of Ge on Si is also realized on Si NIs by using Si_0.5Ge_0.5 buffer.     

Structural properties of SiO2 films prepared by plasma-enhanced chemical vapor deposition

SiO₂ thin films have been prepared by plasma-enhanced chemical vapor deposition from SiH₄ and N₂O precursors by using different values of the N₂O/SiH₄ flow ratio (γ). Rutherford backscattering spectrometry has been employed to obtain the O/Si atomic ratio of the films. Infrared spectroscopy has demonstrated that oxides having the same O/Si atomic ratio are characterized by a different structure. Indeed, from the analysis of the Si–O–Si stretching peaks, we have found that the peak frequency and full-width at half-maximum (FWHM) are dependent on γ. Peak position and FWHM have been used to calculate the bond angle distribution of the films. The results have demonstrated the occurrence of a Si–O–Si bond angle relaxation phenomenon in films deposited by using a larger excess of N₂O.     

Mechanism of selective Si3N4 etching over SiO2 in hydrogen-containing fluorocarbon plasma

This paper describes the mechanism of selective Si₃N₄ etching over SiO₂ in capacitively-coupled plasmas of hydrogen-containing fluorocarbon gas, including CHF₃, CH₂F₂ and CH₃F. The etch rate of Si₃N₄ and SiO₂ is investigated as a function of O₂ percentage in all plasma gases. Addition of O₂ in feed gases causes plasma gas phase change especially H density. The SiO₂ etch rate decreases with increase of O₂ percentage due to the decline of CF_x etchant. The Si₃N₄ etch rate is found to be strong correlated to the H density in plasma gas phase. H can react with CN by forming HCN to reduce polymer thickness on Si₃N₄ surface and promote the removal of N atoms from the substrate. Thus the Si₃N₄ etch rate increases with H intensity. As a result, a relative high selectivity of Si₃N₄ over SiO₂ can be achieved with addition of suitable amount of O₂ which corresponds to the maximum of H density.     

Pulsed semiconductor lasers with higher optical strength of cavity output mirrors

Asymmetric heterostructures with an ultrathick waveguide based on an AlGaAs/GaAs alloy system that allow lasing at a wavelength of 905 nm have been developed and fabricated by hydride metalorganic vapor-phase epitaxy. The internal optical loss and internal quantum efficiency of semiconductor lasers based on such structures were 0.7 cm^-1 and 97%, respectively. It is shown that the highest output optical power of laser diodes with antireflecting (SiO₂) and reflecting (Si/SiO₂) coatings deposited on untreated Fabry-Perot cavity facets obtained by cleaving in an oxygen atmosphere reached 67 W in the pulsed mode and is limited by mirror damage. Treatment of Fabry-Perot cavity facets by etching in argon plasma and the formation of coatings with passivating and oxygen-blocking GaN and Si₃N₄ layers allowed an increase in the maximum output optical power to 120 W. Mirror damage was not observed at the attained output optical power.     

Charge storage by irradiation with UV light in non-biased MNOS structures

Charge storage in non-biased MNOS (Metal-Nitride-Oxide-Semiconductor) structures effected by irradiation with UV light has been investigated. The electrons generated by internal photoemission at the Si surface are trapped at the SiO₂Si₃N₄-interface and inside the Si₃N₄. The resulting charge storage in the insulator can be determined by capacitance technique. The observed positive voltage shift in C-V-characteristics depends on photon energy as well as on radiant exposure. The charge storage occurs in three stpes which can be related to various types of traps. The charged structure can partially be discharged by irradiation with light of less energy than needed for the storage process.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.