Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs

Reconfigurable SRAM-based FPGAs are highly susceptible to radiation induced single-event upsets (SEUs) in space applications.The bit flip in FPGAs configuration memory may alter user circuit permanently without proper bitstream reparation,which is a completely different phenomenon from upsets in traditional memory devices.It is important to find the relationship between a programmable resource and corresponding control bit in order to understand the impact of this effect.In this paper,a method is proposed to decode the bitstream of FPGAs from Xilinx Corporation,and then an analysis program is developed to parse the netlist of a specific design to get the configuration state of occupied programmable logic and routings.After that,an SEU propagation rule is established according to the resource type to identify critical logic nodes and paths,which could destroy the circuit topological structure.The decoded relationship is stored in a database.The database is queried to get the sensitive bits of a specific design.The result can be used to represent the vulnerability of the system and predict the on orbit system failure rate.The analysis tool was validated through fault injection and accelerator irradiation experiment.     

Mitigation of soft errors in SRAM-based FPGAs using CAD tools

This paper presents three methods to reduce the system failures resulted from soft errors: (1) an adaptive redundancy-based method that utilizes unused resources to tolerate the effects of soft errors in SRAM-based FPGAs; (2) an SEU-aware method in CAD flow of SRAM-based FPGAs to mitigate the effects of soft errors which is based on T-VPack and VPR tools and functions without any redundancy; and finally, (3) combination of these two methods to realize whether these SEU reduction methods are cumulative or not when they are applied in sequence. The effects of these methods have been investigated on several MCNC benchmarks. The results show that the system failure rate of circuits implemented on FPGAs decreases about 3.59% using the first method, 4.60%, 10.09%, and 12.45% in three cases of the second method, and 7.47%, 15.94%, and 17.43% in three cases of the third method. These results show that the effect of combining the first and the second methods is cumulative.     

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, the HLS tool from Xilinx is used to generate different design architectures and then analyze the probability of errors in those architectures. Two different case studies scenarios are investigated. First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA. The number of errors classified as silent data corruption and timeout according to the architectures and DSP blocks usage is analyzed. Moreover, more possibilities of HLS designs are explored such as data organization, aggressive pipeline insertion and the implementation of the algorithm in a soft processor like the Microblaze from Xilinx. These architectures are strongly optimized in performance and the least susceptible design under soft errors is investigated. All case-study designs are evaluated in a 28 nm SRAM-based FPGA under fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. The proposed characterization method can be used to guide designers to select better architectures concerning the susceptibility to upsets and performance efficiency.     

实时嵌入式容错系统的关键技术研究

简要回顾了容错技术的发展过程并分析了不同故障模型下系统的客错方式.对于瞬时故障、间歇性故障的容错可采用软件冗余方法,在实时嵌入式系统中采用软件容错时必须考虑任务的可调度性;而永久性故障则采用硬件冗余方法来解决.在此基础上,描述了一种实时双机嵌入式容错系统的模型,研究了构建容错系统需要解决的双机同步、故障检测及仲裁切换等关键问题和相应的解决方法.     

An efficient fault-tolerant multicast routing protocol withcore-based tree techniques

In this paper, we design and analyze an efficient fault-tolerant multicast routing protocol. Reliable multicast communication is critical for the success of many Internet applications. Multicast routing protocols with core-based tree techniques (CBT) have been widely used because of their scalability and simplicity. We enhance the CBT protocol with fault tolerance capability and improve its efficiency and effectiveness. With our strategy, when a faulty component is detected, some pre-defined backup path(s) is (are) used to bypass the faulty component and enable the multicast communication to continue. Our protocol only requires that routers near the faulty component be reconfigured, thus reducing the runtime overhead without compromising much of the performance. Our approach is in contrast to other approaches that often require relatively large tree reformation when faults occur. These global methods are usually costly and complicated in their attempt to achieve theoretically optimal performance. Our performance evaluation shows that our new protocol performs nearly as well as the best possible global method while utilizing much less runtime overhead and implementation cost     

基于双端口SRAM的网闸设计

物理隔离网闸是一种应用级的安全隔离系统,主要用来解决网络安全所带来的问题。基于双端口SRAM的物理网闸隔离系统采用双端口SRAM作为数据交换区,内外网处理单元通过设备驱动接口实现交换区数据的同步访问。该系统具备数据交换快,安全性能高等特点。     

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost.We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.     

Designing pixel-oriented visualization techniques: theory andapplications

Visualization techniques are of increasing importance in exploring and analyzing large amounts of multidimensional information. One important class of visualization techniques which is particularly interesting for visualizing very large multidimensional data sets is the class of pixel-oriented techniques. The basic idea of pixel-oriented visualization techniques is to represent as many data objects as possible on the screen at the same time by mapping each data value to a pixel of the screen and arranging the pixels adequately. A number of different pixel-oriented visualization techniques have been proposed in recent years and it has been shown that the techniques are useful for visual data exploration in a number of different application contexts. In this paper, we discuss a number of issues which are important in developing pixel-oriented visualization techniques. The major goal of this article is to provide a formal basis of pixel-oriented visualization techniques and show that the design decisions in developing them can be seen as solutions of well-defined optimization problems. This is true for the mapping of the data values to colors, the arrangement of pixels inside the subwindows, the shape of the subwindows, and the ordering of the dimension subwindows. The paper also discusses the design issues of special variants of pixel-oriented techniques for visualizing large spatial data sets     

基于SRAM型FPGA的SEU敏感性研究

目前星载信号处理平台中大量使用商用芯片,但商用芯片抗辐射能力较弱,在空间环境下常出现单粒子翻转(Single Event Upset,SEU),从而造成系统功能紊乱,甚至中断。提出以星载信号处理平台中大量使用的SRAM型FPGA为研究对象,采用故障注入的方式研究FPGA中不同硬件资源对于SEU效应的敏感性问题。根据不同资源对SEU效应表现出不同敏感性的结论,可在SRAM型FPGA的抗SEU防护上进行有针对性的设计。     

一种SRAM型FPGA单粒子效应加固平台设计

针对大规模集成电路在空间环境的应用需求,介绍了目前国内外针对FPGA的抗辐射加固的研究现状,对空间辐射和单粒子效应进行了简单描述,分析了SRAM型FPGA的结构和故障特点,提出了一种基于高可靠单元针对Xilinx Kintex-7系列FPGA进行配置、监控、回读校验和刷新的单粒子翻转加固硬件平台设计。介绍了对Kintex-7系列FPGA进行防护的流程和故障注入测试系统的组成,该平台已经在某项目中得到应用并通过了功能测试和相关环境试验,为大规模集成电路在空间应用提供了设计参考。     

A fast partitioning method for PLA-based FPGAs

A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner     

一种Virtex系列FPGA配置数据无损压缩算法

随着FPGA规模大幅度提高,配置数据的规模也迅速增加,从而导致FPGA重构时间的增加,并使得存储多个配置的存储器成为基于FPGA的嵌入式系统成本的最大因素.针对Virtex系列FPGA配置数据的结构特点,提出了一种基于LZW改进的配置数据压缩算法,并通过数字信号处理领域和数字通信领域的5个常用模块进行验证,取得了显著的压缩效果.     

Replica management for fault-tolerant systems

Replication has traditionally been used to assure fault tolerance. Active parallel replication is a new technique that, in addition to ensuring fault tolerance, dramatically reduces computation time and cost     

Universal fault diagnosis for lookup table FPGAs

Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size     

应用于大规模FPGA的解析式布局算法

针对FPGA的结构特点,借鉴ASIC布局算法中非线性建模思想,提出一种应用于大规模FPGA的解析式布局算法.该算法以非线性线长为目标,采用较少迭代次数的共轭梯度方法作为求解器,解决组合优化方法时间大量消耗问题.实验结果表明,该方法能够在较短的时间得到较好的布局质量,与FastPlace的结果对比证明了其有效性.     

一种灵活的包含嵌入式存储器的FPGA结构

近年来,集成电路制造工艺的巨大提高使得FPGA有能力实现大的数字系统电路.这些大的系统通常需要大量的存储器以存储数据.很多FPGA生产商已经推出了含有大的嵌入式存储器的FPGA芯片.然而,大多数学术方面的CAD工具只针对于同质的FPGA结构(即只包括逻辑模块和布线通道的FPGA结构).FPGA的布线结构通常被表示为RRG(布线资源图).本文将介绍一种包含嵌入式存储器模块的FPGA的灵活结构以及一种建立RRG的方法.文中我们对VPR(versatile placingand muting)进行了改进,使得VPR可以处理包含嵌入式存储器结构的FPGA的布局布线问题,同时保持了VPR的灵活性.     

Resource allocation for primary-site fault-tolerant systems

Resource allocation for a distributed system employing the primary site approach for fault tolerance is discussed. Two kinds of systems are considered. The first consists of fault-tolerant nodes where each node has many duplicated servers. One server is the primary, which serves user requests, and the rest are backup. The second does not have fault-tolerant nodes. To tolerate node failures, each node uses other nodes as backups. When a node fails, all requests initially allocated to the node are served by one of its backups. To study the resource allocation for such systems, an approximate model for each system is developed. Using these models, efficient allocation algorithms that take into account the failure/repair rates of the system and the fault-tolerant overheads are presented. Using experimental results, it is shown that the algorithms give the optimal or suboptimal allocations. The algorithms, which incur little overhead, can improve the system performance significantly over an intuitive allocation algorithm     

Software-based rerouting for fault-tolerant pipelined communication

This paper presents a software-based approach to fault-tolerant routing in networks using wormhole or virtual cut-through switching. When a message encounters a faulty output link, it is removed from the network by the local router and delivered to the messaging layer of the local node's operating system. The message passing software can reroute this message, possibly along nonminimal paths. Alternatively, the message may be addressed to an intermediate node, which will forward the message to the destination. A message may encounter multiple faults and pass through multiple intermediate nodes. The proposed techniques are applicable to both obliviously and adaptively routed networks. The techniques are specifically targeted toward commercial multiprocessors where the mean time to repair (MTTR) is much smaller than the mean time between router failures (MTBF), i.e., it is sufficient to tolerate a maximum of three failures. This paper presents requirements for buffer management, deadlock freedom, and livelock freedom. Simulation results are presented to evaluate the degradation in latency and throughput as a function of the number and distribution of faults. There are several advantages of such an approach. Router designs are minimally impacted, and thus remain compact and fast. Only messages that encounter faulty components are affected, while the machine is ensured of continued operation until the faulty components can be replaced. The technique leverages existing network technology, and the concepts are portable across evolving switch and router designs. Therefore, we feel that the technique is a good candidate for incorporation into the next generation of multiprocessor networks