Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs

Reconfigurable SRAM-based FPGAs are highly susceptible to radiation induced single-event upsets (SEUs) in space applications.The bit flip in FPGAs configuration memory may alter user circuit permanently without proper bitstream reparation,which is a completely different phenomenon from upsets in traditional memory devices.It is important to find the relationship between a programmable resource and corresponding control bit in order to understand the impact of this effect.In this paper,a method is proposed to decode the bitstream of FPGAs from Xilinx Corporation,and then an analysis program is developed to parse the netlist of a specific design to get the configuration state of occupied programmable logic and routings.After that,an SEU propagation rule is established according to the resource type to identify critical logic nodes and paths,which could destroy the circuit topological structure.The decoded relationship is stored in a database.The database is queried to get the sensitive bits of a specific design.The result can be used to represent the vulnerability of the system and predict the on orbit system failure rate.The analysis tool was validated through fault injection and accelerator irradiation experiment.     

Mitigation of soft errors in SRAM-based FPGAs using CAD tools

This paper presents three methods to reduce the system failures resulted from soft errors: (1) an adaptive redundancy-based method that utilizes unused resources to tolerate the effects of soft errors in SRAM-based FPGAs; (2) an SEU-aware method in CAD flow of SRAM-based FPGAs to mitigate the effects of soft errors which is based on T-VPack and VPR tools and functions without any redundancy; and finally, (3) combination of these two methods to realize whether these SEU reduction methods are cumulative or not when they are applied in sequence. The effects of these methods have been investigated on several MCNC benchmarks. The results show that the system failure rate of circuits implemented on FPGAs decreases about 3.59% using the first method, 4.60%, 10.09%, and 12.45% in three cases of the second method, and 7.47%, 15.94%, and 17.43% in three cases of the third method. These results show that the effect of combining the first and the second methods is cumulative.     

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, the HLS tool from Xilinx is used to generate different design architectures and then analyze the probability of errors in those architectures. Two different case studies scenarios are investigated. First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA. The number of errors classified as silent data corruption and timeout according to the architectures and DSP blocks usage is analyzed. Moreover, more possibilities of HLS designs are explored such as data organization, aggressive pipeline insertion and the implementation of the algorithm in a soft processor like the Microblaze from Xilinx. These architectures are strongly optimized in performance and the least susceptible design under soft errors is investigated. All case-study designs are evaluated in a 28 nm SRAM-based FPGA under fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. The proposed characterization method can be used to guide designers to select better architectures concerning the susceptibility to upsets and performance efficiency.     

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs

Triple Modular Redundancy is a widely used fault-tolerance methodology for highly-reliable electronic systems mapped on SRAM-based FPGAs. However, the state-of-the-art TMR techniques are unable to effectively deal with cross-domain errors and increased scrubbing time due to growing size of configuration memory. In order to deal with the aforementioned problems, this work proposes a TMR architecture that exploits the fracturable nature of Look Up Tables for simultaneously mapping of majority-voting and error detection at the granularity of TMR domains. An associated CAD flow is developed for partial reconfiguration of TMR domains incorporating changes to the technology mapping, placement and bitstream generation phases. Our results demonstrate that we can achieve significant reduction in repairing times along with better resilience to cross-domain errors with zero hardware overhead compared to the existing TMR methodologies.     

实时嵌入式容错系统的关键技术研究

简要回顾了容错技术的发展过程并分析了不同故障模型下系统的客错方式.对于瞬时故障、间歇性故障的容错可采用软件冗余方法,在实时嵌入式系统中采用软件容错时必须考虑任务的可调度性;而永久性故障则采用硬件冗余方法来解决.在此基础上,描述了一种实时双机嵌入式容错系统的模型,研究了构建容错系统需要解决的双机同步、故障检测及仲裁切换等关键问题和相应的解决方法.     

An efficient fault-tolerant multicast routing protocol withcore-based tree techniques

In this paper, we design and analyze an efficient fault-tolerant multicast routing protocol. Reliable multicast communication is critical for the success of many Internet applications. Multicast routing protocols with core-based tree techniques (CBT) have been widely used because of their scalability and simplicity. We enhance the CBT protocol with fault tolerance capability and improve its efficiency and effectiveness. With our strategy, when a faulty component is detected, some pre-defined backup path(s) is (are) used to bypass the faulty component and enable the multicast communication to continue. Our protocol only requires that routers near the faulty component be reconfigured, thus reducing the runtime overhead without compromising much of the performance. Our approach is in contrast to other approaches that often require relatively large tree reformation when faults occur. These global methods are usually costly and complicated in their attempt to achieve theoretically optimal performance. Our performance evaluation shows that our new protocol performs nearly as well as the best possible global method while utilizing much less runtime overhead and implementation cost     

基于片内SRAM的固态硬盘转换层设计

SSD逐渐成为了存储业界研究的热点.提出基于片内SRAM的flash转换层设计--SBAST,通过SRAM缓存更新的页提高了SSD随机写的效率,并减少了不必要的擦除操作.通过SSDsim的仿真实验,论证了该设计的有效性,给出了后续的计划.     

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost.We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.     

层次式FPGA快速布局算法

随着现代FPGA规模与结构迅速发展,对FPGA物理设计的要求越来越高,为此,对商业化层次式FPGA提出一种快速布局算法.以基于划分的布局方法作为基本算法框架,针对层次式FPGA的结构制定计划分粒度控制、空间分配和线网权重分配等优化策略,对电路划分过程(整体布局过程)和详细布局过程进行优化.实验结果表明,该算法在实现快速布局的同时,嵌入的优化策略平均将总线长缩短29%;与基于结群的层次式FPGA布局算法相比,平均线长仅为基于结群算法的60%,同时平均运行速度快4倍多.     

基于双端口SRAM的网闸设计

物理隔离网闸是一种应用级的安全隔离系统,主要用来解决网络安全所带来的问题。基于双端口SRAM的物理网闸隔离系统采用双端口SRAM作为数据交换区,内外网处理单元通过设备驱动接口实现交换区数据的同步访问。该系统具备数据交换快,安全性能高等特点。     

Designing pixel-oriented visualization techniques: theory andapplications

Visualization techniques are of increasing importance in exploring and analyzing large amounts of multidimensional information. One important class of visualization techniques which is particularly interesting for visualizing very large multidimensional data sets is the class of pixel-oriented techniques. The basic idea of pixel-oriented visualization techniques is to represent as many data objects as possible on the screen at the same time by mapping each data value to a pixel of the screen and arranging the pixels adequately. A number of different pixel-oriented visualization techniques have been proposed in recent years and it has been shown that the techniques are useful for visual data exploration in a number of different application contexts. In this paper, we discuss a number of issues which are important in developing pixel-oriented visualization techniques. The major goal of this article is to provide a formal basis of pixel-oriented visualization techniques and show that the design decisions in developing them can be seen as solutions of well-defined optimization problems. This is true for the mapping of the data values to colors, the arrangement of pixels inside the subwindows, the shape of the subwindows, and the ordering of the dimension subwindows. The paper also discusses the design issues of special variants of pixel-oriented techniques for visualizing large spatial data sets     

一种FPGA抗辐射布线算法设计

随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。     

FPGA的测试

随着ＦＰＧＡ的发展,测试ＦＰＧＡ的技术也得到了相应的发展,出现了不少有关ＦＰＧＡ的测试方面的文献,有些讨论逻辑资源的测试,也有一些讨论连续资源测试。     

基于SRAM型FPGA的SEU敏感性研究

目前星载信号处理平台中大量使用商用芯片,但商用芯片抗辐射能力较弱,在空间环境下常出现单粒子翻转(Single Event Upset,SEU),从而造成系统功能紊乱,甚至中断。提出以星载信号处理平台中大量使用的SRAM型FPGA为研究对象,采用故障注入的方式研究FPGA中不同硬件资源对于SEU效应的敏感性问题。根据不同资源对SEU效应表现出不同敏感性的结论,可在SRAM型FPGA的抗SEU防护上进行有针对性的设计。     

A fast partitioning method for PLA-based FPGAs

A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner     

Universal fault diagnosis for lookup table FPGAs

Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size     

应用于大规模FPGA的解析式布局算法

针对FPGA的结构特点,借鉴ASIC布局算法中非线性建模思想,提出一种应用于大规模FPGA的解析式布局算法.该算法以非线性线长为目标,采用较少迭代次数的共轭梯度方法作为求解器,解决组合优化方法时间大量消耗问题.实验结果表明,该方法能够在较短的时间得到较好的布局质量,与FastPlace的结果对比证明了其有效性.     

一种灵活的包含嵌入式存储器的FPGA结构

近年来,集成电路制造工艺的巨大提高使得FPGA有能力实现大的数字系统电路.这些大的系统通常需要大量的存储器以存储数据.很多FPGA生产商已经推出了含有大的嵌入式存储器的FPGA芯片.然而,大多数学术方面的CAD工具只针对于同质的FPGA结构(即只包括逻辑模块和布线通道的FPGA结构).FPGA的布线结构通常被表示为RRG(布线资源图).本文将介绍一种包含嵌入式存储器模块的FPGA的灵活结构以及一种建立RRG的方法.文中我们对VPR(versatile placingand muting)进行了改进,使得VPR可以处理包含嵌入式存储器结构的FPGA的布局布线问题,同时保持了VPR的灵活性.