Compact NMOS building blocks and a methodology for dedicated digital filter applications

Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.     

High-speed NMOS circuits for ROM-accumulator and multiplier type digital filters

Using a standard 6 /spl mu/m NMOS silicon-gate process, circuit techniques are described for the full integration of high-speed ROM-accumulator and multiplier type digital filters. The ROM-accumulator structure is integrated using a new two-clock four-phase technique which can be used both for ROM and accumulator. An operating speed of 20 Mbits/s is measured. The circuit shows that an eighth-order filter on a 20 mm/SUP 2/ chip, dissipating only 400 mW at 10 Mbits/s is feasible. Using a 4-clock 4-phase technique a 4-bit serial-parallel multiplier is presented featuring 20 Mbits/s operation into a 15 pF load. Power dissipation is 7 mW/cell. Cell area is 0.2 mm/SUP 2/.     

A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

A full-duplex transceiver chip incorporating an adaptive echo canceling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer, and a digital phase locked loop. The authors emphasize system design considerations and a chip architecture minimizing power dissipation, silicon area, and off-chip components. A double poly 3-/spl mu/m CMOS technology is used to implement the 5-V 22-pin device which dissipates less than 50 mW and occupies 27.7 mm/SUP 2/.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A multipurpose micropower SC filter

A design strategy for micropower switched-capacitor filters is presented and illustrated with the design of a multipurpose second-order section. The filter, realized in a double-poly 6-/spl mu/m CMOS process, consumes 237 /spl mu/W if it is used as an equalizer (f/SUB c/=90 kHz, -V/SUB DD/=3 V) and only 72 /spl mu/W if it is used as a bandpass filter for 8 channels (f/SUB c/=192 kHz, V/SUB DD/=3 V). The dynamic range of the filter is over 60 dB and the total chip area is 3.5 mm/SUP 2/, including bonding pads.     

An implantable multielectrode array with on-chip signal processing

This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip.     

A fast 16 bit NMOS parallel multiplier

An architecture for a fast parallel array multiplier is described. Using a 3 /spl mu/m E/D NMOS process, a 16/spl times/16 bit trial circuit has been designed. A multiplication time of 120 ns has been achieved with a power dissipation of 200 mW and a silicon area of 5 mm/SUP 2/. This architecture concept greatly reduces the logical depth of the array by rearranging internal delays. It is applicable in principle to any MOS, CMOS, GaAs, or bipolar technology.     

Micro/370: a 32-bit single-chip microprocessor

A 32-bit single-chip microprocessor is described that directly implements 102 System/370 instructions and supports the emulation of the rest of the instructions. It is fabricated using a 2-/spl mu/m polysilicon-gate NMOS technology with two levels of aluminium. The chip is 10/spl times/10 mm/SUP 2/ with 200000 transistor sites. It is designed for a 10-MHz clock at worst case and has been operated at 18 MHz with a 3-W power dissipation. The design and verification methodologies and the testing consideration are also described.     

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.     

A CMOS line equalizer for a digital subscriber loop

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.     

A 32-bit execution unit in an advanced NMOS technology

The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations and has an on-chip control ROM for instruction decoding. It operates with a single 5-V supply voltage. Measurements resulted in a typical power dissipation of 750 mW and a maximum operation frequency of 6.5 MHz. At this frequency a 32/spl times/32 bit multiplication is performed in less than 5.5 /spl mu/s.     

Circuit techniques for a 25 ns 16K/spl times/1 SRAM using address-transition detection

The authors describe special circuit techniques that have been used to produce a 25-ns HMOS 16K/spl times/1 SRAM. In particular, a new dynamic row-decoder driver, hold-valid-data output driver, and column-decoder driver have been developed. A new memory clear function, called the bulk-write feature, that writes all data locations to the same data as the data-in pin in one long (/spl sime/700 ns) write cycle was also developed. This 16K/spl times/1 SRAM has a die area of 25.3K mil/SUP 2/ (16.3 mm/SUP 2/), and was fabricated using a 2-/spl mu/m double-polysilicon NMOS technology.     

An EEPROM for microprocessors and custom logic

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/.     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

A 32-bit VLSI digital signal processor

A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The architecture is described section by section, and an overview of the instruction set is presented. The extensive design verification process applied to the DSP is also described.     

A 256K dynamic RAM with page-nibble mode

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.     

Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays

The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.