Graded-channel MOSFET (GCMOSFET) for high performance, low voltageDSP applications

Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 μm GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150°C     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

A swing restored pass-transistor logic-based multiply andaccumulate circuit for multimedia applications

Swing restored pass-transistor logic (SRPL), a high-speed, low-power logic circuit technique for VLSI applications, is described. By the use of a pass-transistor network to perform logic evaluation and a latch-type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and accumulate circuit for multimedia applications is implemented in double metal 0.4 μm CMOS technology     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

A VLSI chip set for a large-scale parallel inference machine: PIM/m

The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called `trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 μm double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time     

Manufacturing study of yield and performance dependence on gatelength of submicron AlInAs-GaInAs HEMTs

The fabrication, characterization, and statistical analysis of the performance and yield of AlInAs-GaInAs on InP low-noise high electron mobility transistors (HEMTs) with subquarter-micron T-gates fabricated with electron beam lithography are reported. This was undertaken to establish the manufacturability of submicron AlInAs-GaInAs HEMT technology for various low-noise microwave receiver applications. Excellent DC device yield (up to 90%) was obtained from devices to gate widths 300 μm and 1000 μm. A range of minimum noise figures between 0.026 to 0.5 dB at 2 GHz and 0.39 to 0.8 dB at 12 GHz were obtained for 0.15-μm and 0.20-μm gate length devices. The results establish the correlation between the noise figure and yield for this new class of microwave devices     

A LDMOS technology compatible with CMOS and passive components forintegrated RF power amplifiers

The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPA's) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 3 GHz f _T and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Scalability study of laser-induced vertical make-link structure

The scalability of a direct metal-to-metal connection between two different levels of metallizations has been extrapolated to be compatible with modern semiconductor fabrication technology. A simple equation to evaluate the scalability was formulated based on focused ion beam (FIR) cross-sectional images of larger link structures with various sizes. With a 0.6-μm-thick metal 1 line and a 0.5-μm-thick interlevel dielectric (ILD), a width of less than 0.5 μm is evaluated to be possible for the metal 1 line. Two limitations exist in the process of scaled-down link structures, which are the ratio of the thickness of ILD to the thickness of the metal 1 line, t_ILD/t _m, and the quality of laser beam parameters including the spot size and positioning error. However, modern processing technologies and advanced laser processing systems are considered to allow the scalability of a vertical make-link structure. Two layouts of two-level interconnects were designed with increased interconnect densities with a 1-μm pitch of a 0.5-μm-wide metal 1 line. These results demonstrate the application of commercially viable vertical linking technology to very large-scale integration (VLSI) applications     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

Technology challenges for integration near and below 0.1 μm

Technology challenges for silicon integrated circuits with a design rule of 0.1 μm and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 μm currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 μm which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 μm technology. 0.1 μm technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 μm are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 μm are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 μm is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

A power IC technology with excellent cross-talk isolation

This paper reports a low-cost, excellent cross-talk isolation power integrated circuit (PIG) technology capable of integrating high-voltage LDMOS, high-voltage LIGBT, and low-voltage CMOS control circuit. The technology is implemented using a conventional twin-well CMOS process with no compromise on the CMOS devices, and the breakdown voltages of the LDMOS and LIGBT with drift length of 40 μm are over 400 V. Using this technology, operating current of the body diode of the LDMOS can be improved by over 16 times and operating current of the LIGBT can be improved by over five times before CMOS latch-up in the control circuit occurs     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g_max=198 mS/mm and an I_dast of 0.3 mA/μm at V_g-V_t=1.5 V, with L_G=0.4 μm and t_ox=110 Å. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS     

Neural n-port voltage comparator network

Use is made of a neural architecture to realise a low-offset VLSI implementation of an n-port voltage comparator that performs the winner-take-all function. The circuit has a wide resolution (~50 dB), high gain, and a Hopfield-like positive feedback interconnect matrix, making possible the detection of very small perturbations (<10 mV). The circuit is suitable for applications in Hamming and neural networks, vector quantisers, and other analogue parallel signal processing systems. The performance of the network was measured on a 32 input 2.0 μm CMOS circuit     

Sub-half-micrometer pseudomorphicInP/InxGa1-xAs/InP HEMT's (0.74⩽x⩽0.81)with very high fT values

In the recent past, strained Al-free InP/In_xGa_1-x As/InP high electron mobility transistors (HEMT's) with x>53% and L_G⩾0.5 μm have shown very good performance mainly caused by the exceptional transport properties of electrons in In-rich In_xGa_1-xAs-channel layers. In this letter we report about new results for highly strained devices with L_G<0.5 μm. Thereby, current gain cut-off frequencies of f_T=100 GHz (130 GHz) for x=74% and L_G=0.3 μm at 300 K (80 K) were achieved, respectively, whereas HEMT's with x=81% and L_G=0.18 μm reached f_T=131 GHz (152 GHz) at the same temperatures. Moreover, the same devices showed off- and on-state drain-source breakdown voltages of V_DSbr (OFF)=10.5 and 5 V and V_DSbr (ON)=6 and 4 V, respectively. The combination of good RF and breakdown performance prove the potential of Al-free InP-based HEMT's for power applications at mm-wave frequencies     

An 0.35-μm, 6-mΩ, 43 μΩ-cm2 lateralpower MOSFET for low-voltage, megahertz switching powerapplications

Power MOSFET technology has to be improved significantly in order to address the needs of very low voltage power conversion applications such as that powers the future microprocessor. Detailed studies by the author indicate that device technology that is suitable for this type of application is not the conventional vertical power MOSFET technology; instead, a lateral power MOSFET technology based on the VLSI technology is more suitable. In this letter, we report for the first time the experimental result of a 6-mΩ, 43 μΩ-cm² lateral power MOSFET based on 0.35-μm VLSI design rule. With a gate-charge of only about 3 nC, in terms of on-resistance gate-charge product, these results are the best ever reported for sub-20-V power MOSFET     

High field poling of electrooptic etalon modulators on CMOSintegrated circuits

Reflection etalon modulators with electrooptic polymer layers as the spacer have been fabricated on the surface of a CMOS chip and successfully poled under a dc electric field at 80 V/μm. This is the first demonstration that such etalons can be fabricated on finished VLSI circuits and poled successfully without damage to the electronics while connected to the underlying circuitry. Such modulators, fabricated on the surface of integrated circuits, have potential applications in areas such as optical communication and free-space interconnects for multiprocessors     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.