TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization     

Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

基于SiGe BiCMOS技术的低功耗23G VCO

A 23 GHz voltage controlled oscillator(VCO) with very low power consumption is presented.This paper presents the design and measurement of an integrated millimeter wave VCO.This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator.The VCO RFIC was implemented in a 0.18μm 120 GHz f_t SiGe hetero-junction bipolar transistor(HBT) BiCMOS technology.The VCO oscillation frequency is around 23 GHz,targeting at the ultra wideband(UWB) and short range radar applications.The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around -94 dBc/Hz at a 1 MHz frequency offset.The FOM of the VCO is -177 dBc/Hz.     

Product applications and technology directions with SiGe BiCMOS

In this paper, we highlight the effectiveness and flexibility of SiGe BiCMOS as a technology platform over a wide range of performance and applications. The bandgap-engineered SiGe heterojunction bipolar transistors (HBTs) continue to be the workhorse of the technology, while the CMOS offering is fully foundry compatible for maximizing IP sharing. Process customization is done to provide high-quality passives, which greatly enables fully integrated single-chip solutions. Product examples include 40-Gb/s (OC768) components using high-speed SiGe HBTs, power amplifiers compatible for cellular applications, integrated voltage-controlled oscillators, and very high-level mixed-signal integration. It is argued that such key enablements along with the lower cost and higher yields attainable by SiGe BiCMOS technologies will provide competitive solutions for the communication marketplace.     

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BV_ceo is only defined by the one-dimensional vertical doping profile through the n⁺-emitter, the p-base, the n-intrinsic and the n⁺-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n⁺pn⁻n⁺-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BV_ceo on the transistor gain, doping level and width of the intrinsic collector.     

A high-performance, low-power complementary coupled BiCMOS circuit

Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits     

基于SOI的低功耗智能卡芯片技术

利用SIMOX材料制作智能卡是一种新的技术.本文简要介绍了智能卡的发展及应用,描述了利用SOI(SIMOX)技术制作的新型智能卡芯片,概述了其优点,并分析了现存的问题.     

An overview of smart power technology

The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies     

智能配电、用电远程通信技术分析

针对智能配电、用电系统的远程通信需求,以典型的配电、用电用户需求模型为对象,对SDH/MSTP、工业以太网交换机、EPON技术、GPRS/CDMA技术在同一平台上进行比较分析.通过综合分析推导出各种通信技术的优缺点,并提出了各自的适用范围:工业以太网交换机适合于用户分散的低密度地区接入网建设;SDH/MSTP适合接入容...     

MEMS技术构建更快的"smart"电源芯片

英国初创半导体公司Cambridge Semiconductor(CamSemi)计划推出全新一代的"smart"开关电源器件,将用于离线式变换器与供电应用,并于2005年上半年推向市场.     

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.     

智能家居网络控制器退耦技术应用

针对物联网技术广泛运用,智能家居以及智慧社区的开展,网络控制器广泛应用于室内家用电器和室内外传感器的控制.由于应用领域的特殊性,设计产品必须具有高可靠性和高安全性,需要在具体的试验环境中进行相关的产品测试.通过在具体原理图中退耦技术应用和PCB布局设计,并在具体的电气和环境试验(电脉冲群干扰试验和静电放电试验)中进行分析和总结,对产品进行持续改进,试验后手动和移动控制效果提升明显,设计的产品符合国家标准和企业标准的具体性能要求.本课题退耦技术应用适用于智能家居控制系统中市电电压输入控制的各类触摸控制器.     

Integration of power devices in advanced mixed signal analog BiCMOS technology

This paper outlines lateral power devices in Power BiCMOS (PBC) technologies where increasing application circuit complexity is driving the need to maintain compatibility with advanced CMOS technology and integration by parts remains a challenge. Different device strategies and process roadmaps are required to maintain competitive products. The need for compatibility with these leading edge CMOS technologies complicates the push for reduced complexity. Product application drivers, device styles combined with process integration challenges and methods, and the future problems with shrinking geometry are discussed.     

A complete RF power technology assessment for military applications

During many years, the French MOD has supported technology developments and specific MMICs designs for power amplification from S-band to Ku-band, for radar and electronic warfare applications. Due to critical issues at system level, an independent assessment made in a governmental laboratory was required by program officers in order to check all the key parameters of a new technology. The objective of this paper is to present and analyse data obtained on a PPHEMT technology, simultaneously taking into account technology, microwave measurements and reliability issues. The originality of this work is to gather all these aspects, combined by a new RF life test bench with negative and positive temperatures environment.     

一种基于锗硅双极CMOS工艺的多频段移动电视调谐器芯片

本文给出了一种应用于多频段移动电视调谐器的射频芯片的设计和测试结果。射频调协器由宽带射频前端电路,模拟基带电路,全集成的小数频率综合器和I2C数字接口电路组成。为了满足移动电视标准苛刻的临道抑制指标,同时兼顾低功耗、低成本的要求,本设计采用了带局部自动增益控制的直接下变频接收机方案。为进一步提高临道抑制的性能,基带频道选择滤波器采用了8阶椭圆有源RC的结构,具有阻带衰减高和过渡带极陡的特点。射频调协器芯片采用0.35 μm锗硅双极CMOS工艺制成,硅片面积为5.5 mm2。芯片采用3.0V单电源供电,消耗50mA电流。在CMMB应用中,系统灵敏度达到-97 dBm,临道抑制优于40 dB。     

A SiGe BiCMOS transmitter module for IMT2000 applications

This paper describes a Tx module for IMT2000 applications consisting of an up-conversion mixer and a variable-gain driver amplifier. The up-conversion mixer, based on the Gilbert active topology has a power gain of 4.8 dB and consumes 15-mA current from a 3-V supply. The variable-gain driver amplifier comprises a gain-controlled stage of the current steering structure and a common emitter stage, and has a variable-gain range of over 30 dB with 30.3-mA current consumption. The Tx module achieves a gain error of less than 1.2 dB over a 30-dB gain range, an output IP3 of 25 dBm, and an output PI dB of 7.4 dBm at the maximum gain of 24.5 dB. It occupies 1.0 /spl times/ 1.2 mm.