箝位二极管承受低电压的有源箝位谐振直流环节逆变器

为解决无源箝位谐振直流环节逆变器辅助电路中采用耦合电感辅助换流（即抽头电感法）所引起的箝位二极管两端承受的电压应力过大问题,提出一种箝位二极管承受低电压的有源箝位谐振直流环节逆变器,该逆变器采用有源箝位的方法可使箝位二极管两端承受的最大反向电压不超过直流母线电压的最大值.且该逆变器的辅助谐振电路中只有一个辅助开关器件,箝位电路中无需设置箝位开关,控制简单且硬件成本较低.此外,在箝位电路的作用下可将逆变器的直流母线电压箝位在输入直流电压的1.1~1.3倍,有效地降低了电压应力.以各个阶段下的等效电路为基础,对电路的工作过程进行了分析,并进行了实验验证,实验结果表明开关器件实现了软开关,且在额定功率3kW条件下,逆变器的效率达到96.5%.因此,该拓扑结构能够有效地提高工作效率.     

Quasi-parallel resonant DC link inverter with improved PWMcapability

A quasi-parallel resonant DC-link (QPRDCL) circuit with improved PWM capability is proposed for the zero voltage switching (ZVS) three phase PWM inverter. The circuit has minimum voltage stresses and improved PWM capability due to the flexible selectability of the on/off instants of the resonant link     

A new quasi-resonant DC-link PWM inverter using single switch for soft switching

This paper presents a new quasi-resonant DC-link (QRDCL) inverter. Only one switching device is used to create zero voltage instants under all load conditions. The maximum voltage across the inverter devices is maintained at around (1.01-1.1) times the input source voltage. The circuit has the flexibility of selecting switching instants of the resonant link in synchronism with any PWM technique. Control technique does not require the help of inverter switches to create the zero voltage instants in the DC-link, and voltage and current sensors are eliminated from the control circuit. In this paper, the principle of operation and detailed analysis of the proposed QRDCL inverter are presented and design considerations for achieving soft switching are obtained. Detailed PSPICE simulation studies are carried out to study the feasibility of the proposed topology under various load conditions. The experimental results of the proposed QRDCL PWM inverter feeding a three phase induction motor are given.     

Spectral analysis of a new six-phase pole-changing induction motor drive for electric vehicles

In this paper, a new six-phase pole-changing induction motor drive is proposed to extend the constant-power operating range for electric vehicle application. The double Fourier series is newly employed to analyze the spectra of the motor phase voltage and current. Consequently, the harmonic expression of the inverter DC-link current can be derived. In order to reduce the DC-link harmonics, a new sinusoidal pulsewidth-modulation strategy is developed for the proposed six-phase inverter. Experimental results, particularly the spectra of the phase current and the DC-link current, are given to verify the theoretical analysis.     

A new technique to reject DC-link voltage ripple for invertersoperating on programmed PWM waveforms

A proposal for rejecting DC-link voltage ripple in inverters operating on programmed PWM waveforms is examined in detail. It is demonstrated how continuous elimination of harmonics is achieved at the inverter output while simultaneously rejecting the DC-link voltage ripple. Thus, with the proposed technique, high-quality voltage is guaranteed at the inverter output terminals even with a substantial low-frequency voltage ripple on the DC-link. A thorough modeling of this technique along with the tradeoffs involved in acquiring the immunity to DC-link ripple is illustrated in detail. Potential applications of the technique are in fixed and variable frequency inverters for power supplies and AC motor drives that experience voltage ripple in the DC link such as when fed from a weak AC system that is frequently unbalanced. A design procedure along with the digital implementation of the proposed technique is described. Selected results were verified experimentally on a laboratory inverter     

A novel control scheme for the multilevel rectifier/inverter

A novel three-level pulsewidth modulation (PWM) rectifier/inverter is proposed: this single-phase three-level rectifier with power factor correction and current harmonic reduction is proposed to improve power quality. A three-phase three-level neutral point clamped (NPC) inverter is adopted to reduce the harmonic content of the inverter output voltages and currents. In the adopted rectifier, a switching mode rectifier with two AC power switches is adopted to draw a sinusoidal line current in phase with mains voltage. The switching functions of the power switches are based on a look-up table. To achieve a balanced DC-link capacitor voltage, a capacitor voltage compensator is employed. In the NPC inverter, the three-level PWM techniques based on the sine-triangle PWM and space vector modulation are used to reduce the voltage harmonics and to drive an induction motor. The advantages of the adopted th-ree-level rectifier/inverter are (1) the blocking voltage of power devices (T1, T2, S_a1-S_c4) is clamped to half of the DC-link voltage, (2) low conduction loss with low conduction resistance due to low voltage stress, (3) low electromagnetic interference, and (4) low voltage harmonics in the inverter output. Based on the proposed control strategy, the rectifier can draw a high power factor line current and achieve two balance capacitor voltages. The current harmonics generated from the adopted rectifier can meet the international requirements. Finally, the proposed control algorithm is illustrated through experimental results based on the laboratory prototype.     

A fast dynamic DC-link power-balancing scheme for a PWMconverter-inverter system

The authors propose a new power converter control scheme for a converter-inverter system. The strategy is to fully utilize the inverter dynamics in controlling the converter dynamics. The authors obtain the power dynamics for both converter and inverter systems, and control the converter power so that it matches the required inverter power exactly. Then, in the ideal case, no power flows through the DC-link capacitors and, thus, the DC-link voltage does not fluctuate even though a very small amount of the DC-link capacitance is used. In forcing the converter power to match the inverter power, the authors utilize the master-slave control concept. They control the DC-link voltage level indirectly through the stored capacitor energy in order to exploit the advantage of the linear dynamic behavior of the capacitor energy. This helps them to circumvent a complex control method in regulating the DC-link voltage. Through simulation and experimental results, the superiority of the proposed converter control scheme is demonstrated     

Adaptive SVM to compensate DC-link voltage ripple for four-switchthree-phase voltage-source inverters

An adaptive space vector modulation (SVM) approach to compensate the DC-link voltage ripple in a B4 inverter is proposed and examined in detail. The theory, design, and performance of this pulsewidth modulation (PWM) method are presented, and the method effectiveness is demonstrated by extensive simulations and experiments. High-quality output currents are guaranteed by this approach even with substantial DC-voltage variations that might be caused by an unbalanced AC supply system, the diode rectification of the line voltages, and circulation of one output phase current through the split capacitor bank. The application of this approach to induction machine drives is also discussed. It is concluded that the DC-voltage ripple effect on the B4 inverter output can be minimized by an adaptive SVM algorithm with the advantage of improving the response of the DC-link filter and the output quality of the inverter becoming high     

Soft switching space vector PWM inverter using a new quasi-parallelresonant DC link

A soft switching quasi-parallel resonant DC-link (QPRDCL) inverter with improved PWM capability has been recently presented. The circuit has the minimum voltage stress of the devices and provides the flexibility of selecting the on/off instants of the resonant link, resulting in improved PWM capability. In this paper, the operational principles and the detailed analysis of the QPRDCL inverter are presented for the resonant components design and the inverter control. An SVPWM with optimal vector sequence suitable for the QPRDCL inverter is also presented through the comparisons among five different modified space vector PWM (SVPWM) techniques classified by the voltage vector sequences. The performance of the selected optimal SVPWM is verified by the experimental results     

DC voltage control strategy for a five-level converter

This paper describes a control method for a three-phase five-level diode-clamp pulse width modulation (PWM) converter considering DC-link capacitor voltage balancing problem. The proposed control circuit uses multiband hysteresis comparators (MHCs) to simplify the control of the main circuit. The DC-link capacitor voltage balancing problem is solved by changing the shape of the MHC. The proposed method can (1) overcome voltage imbalance at the DC-link capacitors; (2) achieve a unity power factor; (3) generate nearly sinusoidal input currents; and (4) regenerate electric power back to the power system. Simulation and experimental results demonstrate the validity of the proposed method     

An alternative bus clamp for resonant DC-link converters

This paper presents an alternative circuit configuration for clamping the link voltage in a resonant DC-link converter. The alternative circuit is a lossless clamp which allows for totally autonomous control of the clamp voltage and resonant link under all operating conditions. The clamp is comprised of two capacitors, three controllable switches and three diodes. The clamp does not require the use of external bias supplies for startup or no-load operation. Control of the input and/or output waveforms for a converter employing this circuit remains virtually identical to that for the resonant DC-link inverter (RDCLI). An analysis of clamp operation is performed detailing its modes of operation. From this analysis, insight is gained into the appropriate selection of clamp capacitors. Simulations and experimental results are presented to corroborate the analysis. The control of the clamp is discussed in detail     

Parallel resonant DC link circuit-a novel zero switching losstopology with minimum voltage stresses

A parallel resonant DC link (PRDCL) circuit topology is proposed as an approach to realizing zero switching loss DC-AC high switching frequency power conversion. The proposed circuit is used as an interface between the DC voltage supply and a voltage source pulse width modulated (PWM) inverter to provide a short zero voltage period in the DC link of the inverter to allow zero voltage switchings to take place in the PWM inverter. The peak voltage stress on the PWM inverter switches is limited to the DC supply voltage. Another significant advantage of the circuit is that the inverter can be controlled by the conventional PWM strategy. The proposed circuit is systematically analyzed and its operation principle is explained. Design considerations and design formulas are presented. A complete zero voltage switching DC-AC system consisting of the proposed circuit and a PWM inverter was simulated on a computer     

A new n-level high voltage inversion system

This paper deals with a new multilevel high-voltage source inverter with gate-turn-off (GTO) thyristors. Recently, a multilevel approach seemed to be the best suited for implementing high-voltage power conversion systems because it leads to a harmonic reduction and deals with safe high-power conversion systems independent of the dynamic switching characteristics of each power semiconductor device. A conventional multilevel inverter has some problems; voltage unbalance between DC-link capacitors and larger blocking voltage across the inner switching devices. To solve these problems, the novel multilevel inverter structure is proposed     

Analysis and controller design of static VAr compensator usingthree-level GTO inverter

A static VAr compensator (SVC) using a three-level GTO voltage source inverter (VSI) is presented for high-voltage, high-power applications. The three-level VSI has lower harmonic components and higher DC-link voltage than the two-level VSI and thus can be operated at lower switching frequency (f_sw<500 Hz) without excessive harmonic contents. From the DQ-transformed equivalent circuit of the presented SVC system, DC and AC analyses are carried out to find the steady-state and the dynamic characteristics of the system. Based on the open-loop transfer function of the system, a controller is designed to achieve fast dynamic response. The experimental results confirm the theoretical analyses and controller design     

A Current Distortion Compensation Scheme for Four-Switch Inverters

The four-switch inverter, having a lower number of insulated gate bipolar transistors(IGBTs), has been studied for the possibility of reducing the inverter cost. But it has a limited performance in the low-frequency region, because the balance among the phase currents collapses due to the fluctuation of the center tap voltage of the DC-link capacitors. This problem could be solved if the DC-link capacitance is infinitely large, but it is a costly solution. In this paper, this problem is looked at from the perspective of source impedance and the voltage variation caused by the current flow through the capacitors. The source impedance of the center tap is large compared with other normal IGBT arms. This causes an asymmetry among the three voltage sources, resulting in phase current distortion and unbalance. Second, the capacitor voltage change caused by current flow is another source of current distortion and unbalance. The voltage errors are derived, and based on them, a compensation method is proposed. Effectiveness of the proposed method is demonstrated by the simulation and experimental results.     

A source voltage-clamped resonant link inverter for a PMSM using apredictive current control technique

A simple source voltage-clamped resonant link (SVCRL) inverter is proposed to clamp the DC-link voltage to the input source voltage and reduce the current rating of a resonant inductor. The current control of a permanent magnet synchronous motor (PMSM) employing a predictive current control technique (PCCT) for the SVCRL, inverter is also investigated to overcome the disadvantage of the current-regulated delta modulation (CRDM) control technique. By employing the PCCT based on the discrete model of a PMSM and estimation of back electromotive force (EMF), the minimized current ripple with a small number of switchings can be obtained. Finally, the comparative computer simulation and experimental results are given to show the usefulness of the proposed technique     

A new hybrid active power filter (APF) topology

In this paper, a new hybrid active power filter topology is presented. A higher-voltage, low-switching frequency insulated gate bipolar transistor (IGBT) inverter and a lower-voltage high-switching frequency metal oxide semiconductor field effect transistor (MOSFET) inverter are used in combination to achieve harmonic current compensation. The function of the IGBT inverter is to support utility fundamental voltage and to compensate for the fundamental reactive power. The MOSFET inverter fulfills the function of harmonic current compensation. To further reduce cost and to simplify control, the IGBT and MOSFET inverters share the same DC-link via a split capacitor bank. With this approach harmonics can be cancelled over a wide frequency range. Compared to the conventional APF topology, the proposed approach employs lower dc-link voltage and generates less noise. Simulation and experimental results show that the proposed active power filter topology is capable of compensating for the load harmonics     

Shunt hybrid active power filter under nonideal voltage based on fuzzy logic controller

In this paper, a synchronous reference frame (SRF) method based on a modified phase lock loop (PLL) circuit is developed for a three-phase four-wire shunt hybrid active power filter (APF). Its performance is analysed under unbalanced grid conditions. The dominant lower order harmonics as well as reactive power can be compensated by the passive elements, whereas the active part mitigates the remaining distortions and improves the power quality. As different control methods show contradictory performance, fuzzy logic controller is considered here for DC-link voltage regulation of the inverter. Extensive simulations of the proposed technique are carried out in a MATLAB-SIMULINK environment. A laboratory prototype has been built on dSPACE1104 platform to verify the feasibility of the suggested SHAPF controller. The simulation and experimental results validate the effectiveness of the proposed technique.     

Analysis of a quasi-resonant circuit for soft-switched inverters

This paper presents an analysis of a quasi-resonant circuit for soft-switched inverters. The quasi-resonant circuit provides zero-voltage instants for zero-voltage inverter switching by pulling down the DC link voltage momentarily to zero without increasing the peak value of the nominal DC link voltage. Switches in the quasi-resonant circuit can also be turned off at zero current/voltage conditions. The proposed circuit allows creation of zero voltage conditions for inverter soft-switching under loaded and no-load conditions. The operating principle of this circuit is explained, and the analysis of each operating mode is described. Design criteria for achieving zero voltage switching are derived from the general mathematical analysis. Operation of the circuit has been verified by PSPICE simulation and experiments     

A novel single-stage full-bridge buck-boost inverter

A novel single-stage full-bridge series-resonant buck-boost inverter (FB-SRBBI) is proposed in this paper. The proposed inverter only includes a full-bridge topology and a LC resonant tank without auxiliary switches. The output voltage of the proposed inverter can be larger or lower than the dc input voltage, depending on the instantaneous duty-cycle. This property is not found in the classical voltage source inverter, which produces an ac output instantaneous voltage always lower than the dc input voltage. The proposed inverter circuit topology provides the main switch for turn-on at ZCS by a resonant tank. The nonlinear control strategy is designed against the input dc perturbation and achieves well dynamic regulation. An average approach is employed to analyze the system. A design example of 500 W dc/ac inverter is examined to assess the inverter performance and it provides high power efficiency above 90% under the rated power.