Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/ and SiO/sub 2/ tunneling dielectrics

In this study, we have developed a SiGe dot floating-gate flash memory with high-K dielectric (HfO/sub 2/) tunneling oxide. Using SiGe dots and HfO/sub 2/ tunneling oxide, a low program/erase voltage can be achieved, along with good endurance and charge retention characteristics as compared to the SiGe dots with a SiO/sub 2/ tunneling oxide. We have also examined the impact of Ge concentration in the SiGe dots on charge retention time. This demonstrates that the SiGe dots with HfO/sub 2/ tunneling oxide can be used as the floating gate to replace SiGe dots with SiO/sub 2/ tunneling oxide and have a high potential for further scaling of floating gate memory devices.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Lanthanide (Tb)-doped HfO/sub 2/ for high-density MIM capacitors

A high-density metal-insulator-metal (MIM) capacitor with a lanthanide-doped HfO/sub 2/ dielectric prepared by physical vapor deposition (PVD) is presented for the first time. A significant improvement was shown in both the voltage coefficient of capacitance (VCC) and the leakage current density of MIM capacitor, yet the high capacitance density of HfO/sub 2/ dielectrics was maintained by achieving the doping of Tb with an optimum concentration in HfO/sub 2/. This technique allows utilizing thinner dielectric film in MIM capacitors and achieving a capacitance density as high as 13.3 fF//spl mu/m/sup 2/ with leakage current and VCC values that fully meet requirements from year 2005 for radio frequency (RF) bypass capacitors applications.     

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.     

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

The low-frequency noise has been studied in nMOSFETs with an HfO/sub 2/--SiO/sub 2/ gate stack, for different thickness of the SiO/sub 2/ interfacial layer (IL). It is observed that the 1/f-like noise in linear operation, is about 50 times higher in the HfO/sub 2/ devices with a 0.8-nm chemical oxide IL, compared with the 4.5-nm thermal oxide reference n-channel transistors. This is shown to relate to the correspondingly higher trap density in the dielectric material. In addition, it is demonstrated that the noise rapidly reduces with increasing thickness of the IL. From the results for a 2.1-nm SiO/sub 2/ IL, it is derived that at a certain gate voltage range, electron tunneling to a defect band in the HfO/sub 2/ layer may contribute to a pronounced increase in the flicker noise.     

PVD HfO/sub 2/ for high-precision MIM capacitor applications

Metal-insulator-metal (MIM) capacitors are fabricated using sputtered HfO/sub 2/ with Ta and TaN for top and bottom electrodes, respectively. High-capacitance densities from 4.7 to 8.1 fF//spl mu/m/sup 2/ have been achieved while maintaining the leakage current densities around 1 /spl times/ 10/sup -8/ A/cm/sup 2/ within the normal circuit bias conditions. A guideline for the insulator thickness and its dielectric constant has been obtained by analyzing the tradeoff between the linearity coefficient and the capacitance density.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

MOS Characteristics of synthesized HfAlON-HfO/sub 2/ stack using AlN-HfO/sub 2/

We demonstrate a top-surface aluminized and nitrided HfO/sub 2/ gate dielectric using a synthesis of ultrathin aluminum nitride (AlN) and HfO/sub 2/. The reaction of AlN with HfO/sub 2/ through a subsequent high-temperature annealing incorporates Al and N into an HfO/sub 2/ layer, which results in a synthesis of HfAlON near the top surface of HfO/sub 2/, forming an HfAlON-HfO/sub 2/ stack structure. This approach suppresses interfacial layer growth and improves thermal stability of the dielectric, resulting in significant improvement in leakage current. It also shows no adverse effects caused by N and Al incorporation at the bottom interface.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.