A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

This paper presents a theoretical yield model for area array solder interconnect process. To achieve a successful solder joint, contact between the solder ball and its associated wettable pad area is essential because without contact, the solder ball cannot initiate wetting its associated pad and, finally, is found an open defect. When an area array solder joints are made simultaneously, it may happen that some of the solder joints in a chip cannot make contact with their associated pads because of the variations of design parameters such as solder ball size, pad size and height, substrate warpage, etc. The yield model provides the relationships of the interconnect yield to the statistical variations of the design parameters. A series of experiments were performed with specially designed area array flip-chips and substrates to verify the model, focusing on the effects of the solder ball size variation and the number of solder joints on interconnect yield. The experimental observations agree well with the model prediction.     

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm² Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations.     

Mapping the failure envelope of board-level solder joints

Single solder interconnects were subjected to a series of combined tension-shear and compression-shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability.     

Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

Drop impact reliability of Sn–1.0Ag–0.5Cu BGA interconnects with different mounting methods

The poor drop-shock resistance of near-eutectic Sn–Ag–Cu (SAC) solder interconnects drives the research and application low-Ag SAC solder alloys, especially for Sn–1.0Ag–0.5Cu (SAC105). In this work, by dynamic four-point bend testing, we investigate the drop impact reliability of SAC105 alloy ball grid array (BGA) interconnects with two different surface mounting methods: near-eutectic solder paste printing and flux dipping. The results indicate that the flux dipping method improves the interconnects failure strain by 44.7% over paste printing. Further mechanism studies show the fine interfacial intermetallic compounds (IMCs) at the printed circuit board side and a reduced Ag content inside solder bulk are the main beneficial factors overcoming other negative factors. The flux dipping SAC105 BGA solder joints possess fine Cu₆Sn₅ IMCs at the interface of solder/Cu pads, which increases the bonding strength between the solder/IMCs and the fracture resistance of the IMC grains themselves. Short soldering time of flux dipping joints above the solder alloy liquidus mitigates the growth of interfacial IMCs in size. In addition, a reduced Ag content in flux dipping joint bulk causes a low hardness and high compliance, thus increasing fracture resistance under higher-strain rate conditions.     

Fatigue and Bridging Study of High-Aspect-Ratio Multicopper-Column Flip-Chip Interconnects Through Solder Joint Shape Modeling

This paper addresses fatigue and bridging issues by numerical analysis for an ultra-fine-pitch flip-chip interconnect that consists of multiple copper columns (MCC) and a solder joint. First, the processing flow is briefly presented, which enables prototyping of high-aspect-ratio$(sim hbox6)$copper columns, and hence, enhanced thermomechanical reliability of the interconnects. A public software, Surface Evolver (SE), has been used through this work to predict the solder joint geometry evolution. By integrating SE solder joint shape modeling, stress/strain analysis within ANSYS, and design of experiment (DoE) techniques as well, detailed numerical analysis has been conducted on the solder joint fatigue response to various factors such as the Cu-Solder wetting angle, loading direction, and solder geometry parameters. Finally, by applying the DoE techniques and the most updated features of SE, bridging risks of this interconnect with a fine pitch of 40$mu$m is investigated, in which critical solder volume is calculated as a function of the interconnect geometry parameters. Based on these results, a solid basis for the design and processing of this advanced flip-chip interconnect has been established.     

Ethylene glycol ether free solder paste development

There are growing concerns in the electronics industry for not only finding alternatives to lead but also other potentially hazardous materials as well. This paper summarizes the development of ethylene glycol ether (EGE)-free solder flux for the formulation of lead-free solder pastes. Replacing the toxic components in the flux was only the first challenge, the criteria of commercially proven pastes also had to be met. Both commercial and in-house solder paste formulations were evaluated for printability, reflow, wetting, flux residue removal, and solder void characteristics. Two critical issues, solder bump boids and flux residue removal, were identified and associated with the high temperature reflow of Pb-free pastes. These issues were not effectively improved by the existing commercial EGE-free solder pastes. New solder paste formulations were developed utilizing alternative chemistry than those found in traditional solder paste fluxes. These pastes, some, of which are also water soluble, reduced void frequency and size by more than 4x as compared to vendors' pastes. Solder bump height uniformity of 135 4 m within each die was consistently achieved. Thermal-mechanical reliability tests were performed on various lead-free solder alloys using the new flux formulations. The reliability of flip chip assembled DCA on organic boards with both OSP/Cu and Cu/Ni/au pad metallizations were comparable to eutectic Sn63Pb37 bumped assemblies using commerical pastes.     

Microstructure and reliability of hybrid interconnects by Au stud bump with Sn-0.7Cu solder for flip chip power device packaging

With miniaturization of the interconnect solder bumps, high current density causes serious reliability issues (stress, electromigration etc.) in electronic packages. Through Au stud bumping on the chips and following reflow of solder to produce hybrid interconnects, the eletromigration resistance may be improved by the intermetallics formed inside them due to their barrier effects on the atoms migration. Here, microstructures and reliabilities of Au stud with serial amounts of Sn-0.7Cu solder paste were studied through controlling size of stencil printing aperture. After reflow, AuSn, AuSn₂ and AuSn₄ formed from the surface of Au stud bump to the solder. A layer of (Cu,Au)₆Sn₅ with thickness of 3 μm existed at the interface near the Cu substrate with a scallop shape similar to Cu₆Sn₅. The fraction of intermetallics to the mixed joints varied with the solder amount. Shear strength decreased slightly when comparing with the sole solder joint due to large amounts of brittle intermetallics. Thermal aging resulted in many Kirkendall voids generated at the interfaces of Au stud and the solder, which further decreased the shear strength. The effect of solder amount on microstructural evolution and fracture modes was discussed. The hybrid interconnects showed a good electromigration resistance.     

Effect of Metal Bond-Pad Configurations on the Solder Microstructure Development of Flip-Chip Solder Joints

Various microstructural zones were observed in the solidified solder of flip-chip solder joints with three metal bond-pad configurations (Cu/Sn/Cu, Ni/Sn/Cu, and Cu/Sn/Ni). The developed microstructures of the solidified flip-chip solder joints were strongly related to the associated metal bond pad. A hypoeutectic microstructure always developed near the Ni bond pad, and a eutectic or hypereutectic microstructure formed near the Cu pad. The effect of the metal bond pads on the solder microstructure alters the Cu solubility in the molten solder. The Cu content (solubility) in the molten Sn(Cu) solder eventually leads to the development of particular microstructures. In addition to the effect of the associated metal bond pads, the developed microstructure of the flip-chip solder joint depends on the configuration of the metal bond pads. A hypereutectic microstructure formed near the bottom Cu pad, and a eutectic microstructure formed near the top Cu pad. Directional cooling in the flip-chip solder joint during the solidification process causes the effects of the metal bond-pad configuration. Directional cooling causes the Cu content to vary in the liquid Sn(Cu) phase, resulting in the formation of distinct microstructural zones in the developed microstructure of the flip-chip solder joint.     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

Manufacturing of Cu/electroless nickel/Sn-Pb flip chip solder bumps

A process for manufacturing Cu/electroless Ni/Sn-Pb solder bump is discussed in this paper. An attempt to replace zincation with a Cu film as an active layer for the electroless Ni (EN) deposition on Al electrode on Si wafer is presented. Cu/electroless Ni is applied as under bump metallurgy (UBM) for solder bump. The Cu film required repeated etches with nitric acid along with activation to achieve a satisfactory EN deposit. Fluxes incorporating rosin and succinic acid were investigated for wetting kinetics and reflow effectiveness of the electroplated solder bump. The solder plating current density and the reflow condition for achieving solder bumps with uniform bump height were described. The Cu/EN/Sn-Pb solder system was found to be successfully produced on Al terminal in this study that avoids using zincating process     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Manufacturing of solder bumps with Cu/Ta/Cu as under bumpmetallurgy

This study investigated the feasibility of the multilayer Cu/Ta/Cu under bump metallurgy (UBM), deposited on AlN/Si where AlN is a thin film. An interdiffusion study found that Ta is an appropriate diffusion barrier layer for the investigated solder bump structure. The temperature profiles and the flux compositions for solder reflow were also investigated. The flux activators investigated include succinic acid, adipic acid, stearic acid, dimethylamine hydrochloride, and diethylamine hydrochloride. Among these, succinic acid was the most appropriate in terms of wetting and cleaning     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

Impact of probing procedure on flip chip reliability

Probe-after-bump is the primary probing procedure for flip chip technology, since it does not directly contact the bump pad, and involves a preferred under bump metallurgy (UBM) step coverage on the bump pads. However, the probe-after-bump procedure suffers from low throughputs and high cost. It also delays the yield feedback to the fab, and makes difficult clarification of the accountability of the low yield bumped wafer between the fab and the bumping house. The probe-before-bump procedure can solve these problems, but the probing tips may over-probe or penetrate the bump pads, leading to poor UBM step coverage, due to inadequate probing conditions or poor probing cards. This work examines the impact of probing procedure on flip chip reliability, using printing and electroplating bumpings on aluminum and copper pads. Bump height, bump shear strength, die shear force, UBM step coverage, and reliability testing are used to determine the influence of probing procedure on flip chip reliability. The experimental results reveal that bump quality and reliability test in the probe-before-bump procedure, under adequate probing conditions, differ slightly from the corresponding items in the probe-after-bump procedure. UBM gives superior step coverage of probe marks in both probe-before-bump and probe-after-bump procedures, implying that UBM achieves greater adhesion and barrier function between the solder bump and the bump pad. Both printing and electroplating bump processes slightly influence all evaluated items. The heights of probe marks on the copper pads are 40–60% lower than those on the aluminum pads, indicating that the copper pad enhances UBM step coverage. This finding reveals that adequate probing conditions of the probe-before-bump procedure are suited to sort flip chip wafers and do not significantly affect bump height, bump shear strength, die shear force, or flip chip reliability.     

Reliability issues in Pb-free solder joint miniaturization

As solder joints become increasingly miniaturized to meet the severe demands of future electronic packaging, it is vitally important to consider whether the solder joint size and geometry could become reliability issues and thereby affect implementation of the Pb-free solders. In this study, three bumping techniques, i.e., solder dipping, stencil printing followed by solder reflow, and electroplating of solders with subsequent reflow, were used to investigate the interfacial interactions of molten Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and pure Sn solders on a copper pad at 240°C. The resultant interfacial microstructures, coming from a variety of Cu pads, with sizes ranging from 1 mm to 25 μm, and representing different solder bump geometries, have been investigated. In addition, a two-dimensional thermodynamic/kinetic model has been developed to assist the understanding of the kinetics of interdiffusion and the formation of interfacial intermetallic compounds. Experimental results and theoretical predictions both suggest that the solder bump size and geometry can influence the as-soldered microstructure; therefore, this factor should be taken into consideration for the design of future reliable ultrafine Pb-free solder joints.