VLSI中加法器的一种高效自测试设计

基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关.     

MT-6000中的内建自测试设计

MT-6000是一款时分多路复用串行数据总线控制芯片。其特点是高集成度,高容错性以及在恶劣环境下的高可靠性等。芯片设有内建自测试功能来保障其可用性,同时自测试方法简洁,其功能覆盖达80%以上。研究了MT-6000的系统结构,设计了核心部分的内建自测试,包括自测试码产生方法及自测试电路。最后给出了实验分析结果。     

Built-In Self-Test Structures

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

Built-In Self-Test Techniques

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

Design And Test of the 80386

A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completed in less time than scheduled and set an Intel record for tapeout to mask fabricator. The strategy incorporated both top-down and bottom-up design approaches. The top-down flow was external architectural definition, internal architecture, internal unit RTL (register transfer logic) and finally detailed logic. The bottom-up flow was detailed transistor and cell circuit design and layout, block (ALU, PLA, etc.) circuit design and layout, and finally global circuit design and layout. Testability also played an important part in the design's success. The 80386 combines two forms of designed-in test functions: built-in self-test and test hooks or functions explicitly designed in to aid testing.     

基于FPGA的板级BIST设计和实现策略

为解决复杂电路板的测试问题,边界扫描、内建自测试等可测性设计技术相继发展,针对目前板级可测性设计发展状况,提出了基于FPGA的板级BIST设计策略;通过阐述存储器模块、逻辑模块和模拟模块三大部分的BIST设计,说明了基于FPGA进行板级模块BIST设计的灵活性和优势;最后,给出了在FPGA内构建BIST控制器的方法,并介绍了FPGA自测试的实现以及在板级设计过程中要考虑的问题。     

机载蓄电池地面维护系统自检方法研究

基于机载蓄电池地面维护目标,针对维护系统自身的自检问题,为了保证系统的可靠性、稳定性以及精度,研究了维护系统的自检测方法。以电控柜中常用部件继电器、数字电源、电子负载、电压表为主要检测对象,基于回路设计与返回值的思想,结合计量功能,完成维护系统的自检功能设计与实现。实验结果及现场应用表明,该方法自检成功率达到100%,维护电压、电流精度指标均在0.3%以内,单通道融入自检的维护过程所需时间在1s以内,满足机载蓄电池地面维护现场需求,有效保证维护设备自身的可靠性。     

基于环绕BIT的通用ATS自检设计与实现

为了保证通用ATS中测试资源到通用测试接口间信号传输的可靠性以及通用测试接口上测试资源的可用性,提出了基于环绕BIT技术的ATS自检方案;该自检方案通过分析通用ATS内部各种测试资源的特性,并按照信号的特性以及自检的实际需求进行了分类,充分利用集成芯片设计了各类测试资源相应的自检电路,采用LabWindows/CVI开发了完整的自检软件,并以电源自检为例介绍软件设计;实际证明该方案可以满足通用ATS自检的需求,具有极大的实用价值.     

ScanBist: a multifrequency scan-based BIST method

The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode     

MIND: An inside Look at an Expert System for Electronic Diagnosis

Because of its intended purpose, it is very complicated to diagnose faults in VLSI test system hardware. When this problem is considered in the hardware design phase, it is apparent that VLSI test systems need to have built-in self-test features. For a self-test to be of any value, the circuit check program should minimize the hardware involved in each test. MIND is an expert system for VLSI test system diagnosis that integrates the principles of their hierarchical design and experts' heuristics to achieve a practical approach to reducing test system downtime.     

芯片级BIST控制器的设计与实现

为适应某型国产航电设备故障的实时自检测及定位需要,设计一个针对自测试电路的芯片级BIST控制器。传统的测试方法存在测试时间长和故障覆盖率不高的缺点。为此,采用伪随机测试向量和确定性测试向量相结合的混合BIST技术及多扫描链、压缩向量技术,对芯片级BIST控制器进行研究,给出功能模块的设计方案。利用Quartus II软件对设计进行仿真,测试结果证实该设计可达到某型航电设备的故障自检测要求。     

Serial interfacing for embedded-memory testing

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable     

大型机电设备故障诊断装置自检的实现

为了提高大型机电设备故障诊断装置诊断结果的可靠性,给诊断装置增加了较完善的自检功能。本文重点论叙了诊断装置中的IO板部分、A/D板部分、液体摆调平部分及其相关电路自检的软、硬件实现。     

基于VXI总线的动态驱动开关模块研究

为了解决传统静态驱动开关阵列模块集成度低的问题,在深入分析静态驱动和动态驱动优缺点的基础上,设计了一种动态驱动的开关阵列模块;简要介绍了VXI总线接口电路的设计方法,重点介绍了模块功能电路的设计,包括动态驱动电路设计、自检电路设计和模块的软件设计;实践应用表明,该模块性能稳定、应用灵活、具有较高的经济实用价值。     

逻辑内建自测试技术进展综述

逻辑内建自测试(logic buit-in self-test,LBIST)是一种可测试性设计技术,利用芯片、板级或系统上的部分电路测试数字逻辑电路本身。LBIST对于许多应用来说至关重要,尤其是国防、航空航天、自动驾驶等生命和任务关键型的应用。这些应用需要执行片上、板上或系统内自检,以提高整个系统的可靠性及执行远程诊断的能力。该文首先给出了常用的LBIST分类,并描述了经典的,也是工业界应用最成功的LBIST架构——使用多输入特征寄存器和并行移位序列产生器的自测试架构;其次,对国内外研究团队、研究进展进行了总结;再次,详细剖析了LBIST的基本原理、时序控制、确定性自测试设计、低功耗设计、“X”容忍等关键技术点,列举出了主流的LBIST商业工具,并逐一分析了其软件架构和技术特点;最后,讨论当前LBIST技术仍需进一步解决的问题,并进行展望。     

Automated BIST for sequential logic synthesis

An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone     

一种新的缩短自测试序列长度的方法

本文建立在逻辑电路内部自测试的基础上，提出了一种新的缩短伪随机测试序列长度的方法。文中首先找到了最难测故障在电路中的分布，建立了对应于最难测故障的电路模型，然后用线性反馈移位寄存器对这些电路模型的输出信号进行压缩，通过分析压缩后的特征码，得出最难测故障的测试长度。最后利用电路的原始输入概率与测试长度之间的关系，提出了一种缩短测试序列长度的算法，求出了最短的测试长度与最佳的输入概率。     

雷电及地面电场监测一体机的设计研究

设计了一种雷电及地面电场监测一体机,包括地面电场监测单元、雷电探测单元和信号与数据处理单元。地面电场监测单元包括MCU模块、电场仪、放大器、滤波器和自检/自校模块;雷电探测单元包括天线组件、3个前置放大电路、3个信号调理电路、波形鉴别电路、光电管和光探测模块;信号与数据处理单元对前述接收的信号进行处理,并通过通信接口传送给计算机进行显示。此装置将雷电预测和雷电定位功能集成于一体,克服单一设备不易携带、探测精度低的缺点,提高雷电监测精度和准确度。     

基于B/S模式的《计算机应用基础》自测、考试系统功能设计

本文提出了基于目前流行的B/S结构,开发《计算机应用基础》自测、考试系统.该系统应由两大部分和三大功能模块组成.其中两大部分别为前台自测、考试部分和后台数据管理部分,而三大功能模块分别是系统管理员模块、学生模块和教师模块.该系统能实现用户远程登录、注册,用户管理,学生自测、在线考试、成绩管理、自动随机组卷等功能.