Area Minimization of Exclusive-OR Intensive Circuits in FPGAs

This paper presents Exclusive-OR (XOR)-based decomposition methods to implement XOR-intensive circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannons expansion theorem. Such extension enables us to force decomposing the original circuits into the smaller sub-circuits. The second proposed method is based on the Exclusive-or-Sum-Of-Products (ESOP) expression that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the XOR-intensive circuits. The Microelectronics Center of North Carolina (MCNC) benchmark circuits are used to demonstrate the effectiveness of the proposed techniques. The proposed ESOP expression method is superior to the other common techniques in achieving realization efficiency. The proposed ESOP expression method needs 8.08 extra CLBs on average to implement the parity functions of the MCNC benchmark circuits while the typical method needs 14.31 extra CLBs on average. In other words, when using the proposed ESOP expression method, the number of CLBs is reduced by 34% compared to the typical method.     

Thermal Management of On-Chip Caches Through Power Density Minimization

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can be suboptimal when thermal effects are considered. Then, we propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which then exponentially reduces the leakage. Thus, leakage power of the active parts is reduced in addition to the power eliminated from the parts that are turned off. Simulations based on SPEC2000, NetBench, and MediaBench applications in a 70-nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of the caches to maximize the distance between blocks with consecutive addresses. Because of spatial locality, blocks with consecutive addresses are likely to be accessed within a short time interval. By maximizing the distance between such blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they result in a significant reduction in the total energy consumption of a cache     

新型毛刺电压检测电路设计与实现

随着电网的信息化、数字化、自动化和互动化的发展,要求智能电网能够通过电子终端将用户之间、用户和电网公司之间形成网络互动和即时连接,实现数据实时、高速的采集和读取。网络的互联和信息的采集因受到越来越多的安全攻击而面临着信息安全问题。毛刺电压攻击是最常见的一种故障注入攻击方式,它是通过突然改变供电电压的方式对安全设备进行恶意攻击,使其进入错误运行状态进而获得其所包含的机密信息。该方案提出了一种针对毛刺电压攻击的防御电路,该电路首先将毛刺电压采集进来;其次对该毛刺电压进行运算处理,将处理之后的毛刺电压和基准电压进行比较来判断该攻击是否构成攻击;最后将构成攻击的报警信号锁存以供系统进行处理。通过数学运算和实际电路仿真得出,本电路具有不受被攻击电压直流值的影响、功耗小、检测毛刺电压信号的频率范围宽的特点。因此,可以广泛应用于智能卡、智能终端和电力采集终端中,避免了在信息采集的过程中由于受到毛刺电压攻击而造成信息泄露。     

基于动态反馈与功率分配的干扰对齐方法

在多用户MIMO系统中,信道状态的精确性严重影响干扰对齐技术的性能。该文针对信道状态信息(CSI)有限反馈导致的干扰泄露问题,提出一种基于动态反馈与功率分配的干扰对齐方法。首先从理论上分析了系统和速率与信道状态反馈比特分配和功率分配之间的关系,得到了在动态反馈和功率分配条件下系统和速率的解析表达式;在此基础上,以系统容量提升为目标,对反馈比特分配和功率分配优化问题进行建模;并根据信道的准静态特性利用库恩塔克条件(KKT)对该问题进行求解,得到功率和反馈比特分配方案。仿真结果表明,与单独考虑信道状态动态反馈条件下的干扰对齐技术相比,提出的方法能够有效减少干扰泄漏强度,提高系统和速率。     

FPGA和ASIC的电源管理方案

在 FPGA或 ASIC 系统设计中,电源管理是特别需要慎重考虑的关键问题之一。由于不同的系统有不同的要求,再加上 FPGA或ASIC的复杂性和利用率也不尽相同,因此,最佳的电源配置也各不相同。本文介绍了在 FPGA 和 ASIC 的电源管理设计中需要考虑的一些问题。     

一种基于动态功率分配的干扰对齐优化方法

干扰对齐是解决无线通信系统中同频干扰的有效手段,显著地提高了多小区MIMO系统的容量。为了解决常规干扰对齐算法只在空间域上对齐的不足,提出一种联合功率分配的干扰对齐优化方案。基于信道矩阵的弦距离计算和优化干扰对齐方案的预编码矩阵;然后在用户的各个数据流之间进行动态功率分配,使干扰进一步减小。仿真结果表明,相比已有的预编码矩阵设计方案,系统容量有明显的改进,降低了系统误码率,具有良好的工程适用性。     

最小风险的Naive Bayes技术在反垃圾邮件系统中的应用

文章提出了一套更好地过滤中文垃圾邮件的方案，这套方案将利用垃圾邮件规律的规则过滤和最小风险的Naive Bayes内容过滤算法结合了起来，并根据垃圾邮件的特性做了必要的改进。并且这套方案也在Linux／Solaris系统平台下基本上完成了大部分功能的软件编程。实际电子邮件服务器上对本方案进行了测试．结果显示这套方案取得了很好的过滤效果。最小风险的Naive Bayes技术是目前最重要的反垃圾邮件技术之一。     

Total Power Modeling in FPGAs Under Spatial Correlation

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.      

CMOS集成电路中Glitch Power的分析方法研究

在集成电路中器件延迟数学模型的基础上,介绍了如何利用定时布尔函数和定时有序二值决策图对集成电路Glitch Power进行分析;借助CUDD软件包,构建了电路的Timed-OBDD表达形式,对一些典型的BenchMark进行了仿真.     

Scientific Workflow Makespan Minimization in Edge Multiple Service Providers Environment

The edge computing model offers an ultimate platform to support scientific and real-time workflow-based applications over the edge of the network. However, scientific workflow scheduling and execution still facing challenges such as response time management and latency time. This leads to deal with the acquisition delay of servers, deployed at the edge of a network and reduces the overall completion time of workflow. Previous studies show that existing scheduling methods consider the static performance of the server and ignore the impact of resource acquisition delay when scheduling workflow tasks. Our proposed method presented a meta-heuristic algorithm to schedule the scientific workflow and minimize the overall completion time by properly managing the acquisition and transmission delays. We carry out extensive experiments and evaluations based on commercial clouds and various scientific workflow templates. The proposed method has approximately 7.7% better performance than the baseline algorithms, particularly in overall deadline constraint that gives a success rate.

     

无线供能移动边缘网络中计算时延最小化资源分配方法研究

针对无线供能移动边缘计算(MEC)网络,该文将计算时延定义为数据卸载与计算所消耗的时间,并提出一种节点计算时延之和最小化的多维资源分配方法。首先,在节点能量因果约束下,通过联合优化专用能量站工作时长、任务分割系数、节点计算频率和发射功率来建立一个计算时延之和最小化的多维资源分配问题。由于存在优化变量耦合与max-max函数,所建问题非凸且无法采用凸优化工具获取最优解。为此,通过引入一系列松弛变量和辅助变量来进行优化问题简化以及优化变量解耦,并在此基础上,通过深入分析简化问题的结构特性,提出一种基于二分法的迭代算法来求解原问题的最优解。最后,计算机仿真验证了所提迭代算法的正确性以及所提资源分配方法在计算时延方面的优越性。     

Smart Edge Caching-Aided Partial Opportunistic Interference Alignment in HetNets

The development of the next-generation wireless networks are regarded as the essentials to embrace of Internet of Things (IoT) and edge computing in heterogeneous networks (HetNets). Due to the the spectrum scarcity problem and the large number of connectivity demand of IoT users, intelligent interference management for IoT is worthy of thorough investigation and should be well discussed with consideration on edge computing in heterogeneous networks (HetNets). Two crucial challenges in the context are: 1) placing edge cache based on dynamic request of IoT users, and 2) cache-enabled interference management with time-varying wireless channels. In this paper, we proposed smart edge caching-aided partial opportunistic interference alignment(POIA) with deep reinforcement learning for IoT downlink system in HetNets. Towards this end, the proposed scheme can update the base station (BS) cache dynamically, and then select the optimal cache-enabled POIA user group considering the time-varying user’s requests and time-varying wireless channels. To solve this problem efficiently, the reinforcement learning is exploited that can take advantage of a deep Q-learing to replace the system action. Extensive evaluations demonstrate that the proposed method is effectiveness according to sum rate and energy efficiency of IoT downlink transmission for HetNets.

     

Joint Power Minimization in Wireless Relay Channels

Energy-constrained multihop wireless links are considered, where the total power consumption is minimized under given requirements on the end-to-end bit error rate (BER). As multihop transmissions are known to be able to save transmission energy in a wireless environment, we study the optimal power scheduling schemes over intermediate hops when the source- relays-destination link can be modeled as cascaded binary symmetric channels. The problem is formulated with an end- to-end BER constraint, and the resulting power consumption is compared with that of the individual link requirement strategy where each hop assigns power under a per-link BER constraint. Results show that the proposed joint power scheduling strategy can achieve a maximum power reduction factor of M in an M-hop route.     

车用FPGA解决方案

分析家估计，汽车远程通信业务和硬件的总收益将干未来五年内超越200亿美元，而电子元件供应商正积极投资开发这个新兴而迅速扩张的市场。总体来说，汽车电子有望成为半导体行业的一个亮点，带领整个行业走出谷底．想想令天在路上行驶的汽车总教，就知道汽车电子的市场发展潜力实在惊人，新一代的汽车电子器件还有庞大的发展空间。随着汽车制造商集成各种新颖的乘客安全，舒适、信息和远程信息处理设备，元器件供应商正将业界的设计挑战转化为获得可观收益的良机。     

基于边缘算力协同系统的视频智能分析任务动态调度方法

对监控视频数据进行基于深度学习模型的智能分析可提升文物博物馆单位的文物安全风险防范能力。针对文物博物馆单位希望充分利用现有空闲可用计算资源完成更多视频数据智能分析的需求,该文提出一种视频智能分析任务动态调度方法,将边缘侧文物博物馆单位内拥有空闲可用计算资源的设备作为计算节点组建边缘算力协同系统进行视频智能分析任务的处理。该文把要解决的问题建模为2维多重背包问题,并采用动态规划的方法,求解如何在边缘算力协同系统上动态分配视频分析任务使得每一个时间周期内系统执行任务获得的安全价值效益最大化的问题。仿真实验结果表明,所提方法能在不干扰文物博物馆单位正常业务应用服务的情况下,根据对系统当前资源使用状态监控与分析,动态分配视频智能分析任务,达到了最大化安全价值效益的目的。     

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.     

X光序列图像三维动态滤波技术

对于静态X光图像序列,帧间滤波技术是抑制噪声、提高信噪比最为有效的方法之一。然而对于活动图像序列,该技术会使运动目标模糊,从而使图像质量更差。本文提出了一种X光序列图像的三维动态滤波技术,把图像序列作为二维空间数据流,在时间上采用先进先出的方式在整个积分周期内进行多帧平均,实现了沿着运动轨迹进行帧间滤波,从而使多帧平均技术对于活动X光图像序列同样具有较好的处理效果。     

系留无人机系统电磁兼容性分析及整改

针对某系留无人机超短波侦察接收系统,实际使用效果不理想的电磁兼容性问题进行分析排查整改。由于无人机系统自身产生的干扰噪声被系统的天线接收到,从而导致该系统出现电磁干扰问题影响使用性能。针对系统出现的电磁干扰问题进行了详细的分析排查,并采取相应的整改措施。整改后,系统电磁干扰明显降低,性能明显提升,达到预期效果,为此类设备的电磁兼容设计整改提供一定的参考。