Area Minimization of Exclusive-OR Intensive Circuits in FPGAs

This paper presents Exclusive-OR (XOR)-based decomposition methods to implement XOR-intensive circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannons expansion theorem. Such extension enables us to force decomposing the original circuits into the smaller sub-circuits. The second proposed method is based on the Exclusive-or-Sum-Of-Products (ESOP) expression that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the XOR-intensive circuits. The Microelectronics Center of North Carolina (MCNC) benchmark circuits are used to demonstrate the effectiveness of the proposed techniques. The proposed ESOP expression method is superior to the other common techniques in achieving realization efficiency. The proposed ESOP expression method needs 8.08 extra CLBs on average to implement the parity functions of the MCNC benchmark circuits while the typical method needs 14.31 extra CLBs on average. In other words, when using the proposed ESOP expression method, the number of CLBs is reduced by 34% compared to the typical method.     

Thermal Management of On-Chip Caches Through Power Density Minimization

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can be suboptimal when thermal effects are considered. Then, we propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which then exponentially reduces the leakage. Thus, leakage power of the active parts is reduced in addition to the power eliminated from the parts that are turned off. Simulations based on SPEC2000, NetBench, and MediaBench applications in a 70-nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of the caches to maximize the distance between blocks with consecutive addresses. Because of spatial locality, blocks with consecutive addresses are likely to be accessed within a short time interval. By maximizing the distance between such blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they result in a significant reduction in the total energy consumption of a cache     

一种基于动态功率分配的干扰对齐优化方法

干扰对齐是解决无线通信系统中同频干扰的有效手段,显著地提高了多小区MIMO系统的容量。为了解决常规干扰对齐算法只在空间域上对齐的不足,提出一种联合功率分配的干扰对齐优化方案。基于信道矩阵的弦距离计算和优化干扰对齐方案的预编码矩阵;然后在用户的各个数据流之间进行动态功率分配,使干扰进一步减小。仿真结果表明,相比已有的预编码矩阵设计方案,系统容量有明显的改进,降低了系统误码率,具有良好的工程适用性。     

FPGA和ASIC的电源管理方案

在 FPGA或 ASIC 系统设计中,电源管理是特别需要慎重考虑的关键问题之一。由于不同的系统有不同的要求,再加上 FPGA或ASIC的复杂性和利用率也不尽相同,因此,最佳的电源配置也各不相同。本文介绍了在 FPGA 和 ASIC 的电源管理设计中需要考虑的一些问题。     

最小风险的Naive Bayes技术在反垃圾邮件系统中的应用

文章提出了一套更好地过滤中文垃圾邮件的方案，这套方案将利用垃圾邮件规律的规则过滤和最小风险的Naive Bayes内容过滤算法结合了起来，并根据垃圾邮件的特性做了必要的改进。并且这套方案也在Linux／Solaris系统平台下基本上完成了大部分功能的软件编程。实际电子邮件服务器上对本方案进行了测试．结果显示这套方案取得了很好的过滤效果。最小风险的Naive Bayes技术是目前最重要的反垃圾邮件技术之一。     

CMOS集成电路中Glitch Power的分析方法研究

在集成电路中器件延迟数学模型的基础上,介绍了如何利用定时布尔函数和定时有序二值决策图对集成电路Glitch Power进行分析;借助CUDD软件包,构建了电路的Timed-OBDD表达形式,对一些典型的BenchMark进行了仿真.     

Total Power Modeling in FPGAs Under Spatial Correlation

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.      

Scientific Workflow Makespan Minimization in Edge Multiple Service Providers Environment

The edge computing model offers an ultimate platform to support scientific and real-time workflow-based applications over the edge of the network. However, scientific workflow scheduling and execution still facing challenges such as response time management and latency time. This leads to deal with the acquisition delay of servers, deployed at the edge of a network and reduces the overall completion time of workflow. Previous studies show that existing scheduling methods consider the static performance of the server and ignore the impact of resource acquisition delay when scheduling workflow tasks. Our proposed method presented a meta-heuristic algorithm to schedule the scientific workflow and minimize the overall completion time by properly managing the acquisition and transmission delays. We carry out extensive experiments and evaluations based on commercial clouds and various scientific workflow templates. The proposed method has approximately 7.7% better performance than the baseline algorithms, particularly in overall deadline constraint that gives a success rate.

     

Smart Edge Caching-Aided Partial Opportunistic Interference Alignment in HetNets

The development of the next-generation wireless networks are regarded as the essentials to embrace of Internet of Things (IoT) and edge computing in heterogeneous networks (HetNets). Due to the the spectrum scarcity problem and the large number of connectivity demand of IoT users, intelligent interference management for IoT is worthy of thorough investigation and should be well discussed with consideration on edge computing in heterogeneous networks (HetNets). Two crucial challenges in the context are: 1) placing edge cache based on dynamic request of IoT users, and 2) cache-enabled interference management with time-varying wireless channels. In this paper, we proposed smart edge caching-aided partial opportunistic interference alignment(POIA) with deep reinforcement learning for IoT downlink system in HetNets. Towards this end, the proposed scheme can update the base station (BS) cache dynamically, and then select the optimal cache-enabled POIA user group considering the time-varying user’s requests and time-varying wireless channels. To solve this problem efficiently, the reinforcement learning is exploited that can take advantage of a deep Q-learing to replace the system action. Extensive evaluations demonstrate that the proposed method is effectiveness according to sum rate and energy efficiency of IoT downlink transmission for HetNets.

     

车用FPGA解决方案

分析家估计，汽车远程通信业务和硬件的总收益将干未来五年内超越200亿美元，而电子元件供应商正积极投资开发这个新兴而迅速扩张的市场。总体来说，汽车电子有望成为半导体行业的一个亮点，带领整个行业走出谷底．想想令天在路上行驶的汽车总教，就知道汽车电子的市场发展潜力实在惊人，新一代的汽车电子器件还有庞大的发展空间。随着汽车制造商集成各种新颖的乘客安全，舒适、信息和远程信息处理设备，元器件供应商正将业界的设计挑战转化为获得可观收益的良机。     

X光序列图像三维动态滤波技术

对于静态X光图像序列,帧间滤波技术是抑制噪声、提高信噪比最为有效的方法之一。然而对于活动图像序列,该技术会使运动目标模糊,从而使图像质量更差。本文提出了一种X光序列图像的三维动态滤波技术,把图像序列作为二维空间数据流,在时间上采用先进先出的方式在整个积分周期内进行多帧平均,实现了沿着运动轨迹进行帧间滤波,从而使多帧平均技术对于活动X光图像序列同样具有较好的处理效果。     

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.     

系留无人机系统电磁兼容性分析及整改

针对某系留无人机超短波侦察接收系统,实际使用效果不理想的电磁兼容性问题进行分析排查整改。由于无人机系统自身产生的干扰噪声被系统的天线接收到,从而导致该系统出现电磁干扰问题影响使用性能。针对系统出现的电磁干扰问题进行了详细的分析排查,并采取相应的整改措施。整改后,系统电磁干扰明显降低,性能明显提升,达到预期效果,为此类设备的电磁兼容设计整改提供一定的参考。     

反应离子刻蚀中的边缘效应及其补偿办法

在反应离子刻蚀中,可以通过提高刻蚀功率来提高反应离子刻蚀速率,但此时由于反应气体浓度分布的影响,Si片中央和边缘的刻蚀速率存在着明显的差异,刻蚀量偏差最多可达±15%以上.本文分析了反应离子刻蚀中不均匀性的产生机理,并通过实验予以验证.进而提出了通过合理设计掩模图形,以减少边缘效应,从而得到均匀刻蚀结果的补偿方法.实验表明,这种补偿方法在刻蚀速率提高近3倍的同时,可以将不均匀性降至±5%以下,适用于对微结构的均匀性要求较高的场所.     

Minimization of Wireless Sensor Network Energy Consumption Through Optimal Modulation Scheme and Channel Coding Strategy

Wireless sensor networks (WSNs) are composed of sensor nodes generally powered by batteries, for which recharging or replacement is difficult. Since battery technology has not progressed as rapidly as semiconductor technology, energy efficiency has become increasingly important in WSN. On the other hand, data exchanged between nodes are vulnerable to corruption by errors induced by random noise, signal fading and other factors. Therefore, improving link reliability and reducing energy consumption are prime concerns in the design of wireless sensor networks. In this context, performing optimal modulation schemes with suitable channel coding process is a crucial task at the physical layer of this class of networks. This paper investigates the best modulation strategy to minimize the total energy consumption required to send a given number of bits. Energy consumption with both uncoded and coded modulation techniques including M-ary QAM (MQAM), M-ary PSK (MPSK), M-ary FSK (MFSK) and MSK is analytically analyzed and simulated over transmission time, modulation rate and transmission distance. A comparative analysis in terms of energy consumption and probability of Bit Error Rate (BER) referring to MSK modulation with proper Error Control Codes (ECC) approach is presented in this paper. We show that the gain achieved with coded MSK scheme is very promising for obtaining optimal energy network consumption.     

Filtering Allocation in Teletext Data Transmission Under Power and Peak Constraints

Various pulse shapes have been proposed for teletext data transmission. The effect of apportioning the different pulse shapes between the transmitter and the receiver is studied for the cases of a constraint on the power and a constraint on the peak value of the channel signal.     

Throughput Enhancement Through Dynamic Fragmentation in Wireless LANs

Many rate-adaptive MAC protocols have been proposed in the past for wireless local area networks (LANs) to enhance the throughput based on channel information. Most of these protocols are receiver based and employ the RTS/CTS collision avoidance handshake specified in the IEEE 802.11 standard. However, these protocols have not considered the possibility of bursty transmission of fragments in the corresponding rate adaptation schemes. In this article, a rate-adaptive protocol with dynamic fragmentation is proposed to enhance the throughput based on fragment transmission bursts and channel information. Instead of using one fragmentation threshold in the IEEE 802.11 standard, we propose to use multiple thresholds for different data rates so more data can be transmitted at higher data rates when the channel is good. In our proposed scheme, whenever the rate for the next transmission is chosen based on the channel information from the previous fragment transmission, a new fragment is then generated using the fragment threshold for the new rate. In this way, the channel condition can be more effectively used to squeeze more bits into the medium. We evaluate this scheme under a time-correlated fading channel model and show that the proposed scheme achieves much higher throughput than other rate-adaptive protocols.     

非挥发性反溶丝FPGA的设计安全性

掩膜成本升高和日渐增加的最小批量要求是当前半导体业界的两种趋势,使FPGA比与其竞争的ASIC具有更高成本效益。这两种趋势还使得FPGA的市场份额,及以FPGA实现的设计的“价值”不断增加。随着FPGA设计“价值”的增加,对于FPGA的“设计安全性”的需求也在增加。使FPGA的设计安全性至少应达到ASIC技术的水平。