一种65nm CMOS工艺的6-bit时间交替ADC设计

描述了一种改进计时的基于65nm CMOS工艺的6位流水线模数转换器（ADC）实例。采用4个通道均由一个标有刻度的全动态流水线式二分查找 (PLBS)架构,并在折叠前端采用基于25%工作周期的计时同步方案,可将ADC转换率提高至3 GS/s,其功率损耗为4.1 mW。ADC实测结果,在低输入频率条件下测得的无杂散动态范围(SFDR)和信噪失真比（SNDR）分别为44.1和31.2 dB。与类似高速ADC相比,该设计将PLBS架构的速度提高了60%,同时也提高了ADC的功率效率。模数转换器原型核心电路面积为250 × 120 μm2。     

1.8 V 10 bit 40 MS/s的流水线模数转换器

设计了一个10 bit,40 MS/s流水线模数转换器,适用于无线传感器网络(WSN)嵌入式芯片中.基于对电容失配的非线性影响的分析,提出了每级多比特的结构,使ADC具有很好的线性度.片内集成了参考电压源,大大减少了外围电路的数量.芯片采用SMIC 0.18μm CMOS工艺实现,在40 MS/s采样率下,电路微分非线性(DNL)最大0.42 LSB,积分非线性(INL)最大0.93 LSB,有效精度(ENOB)最高达9 bit.电路使用1.8 V电压供电,核心面积1.5mm2,核心电路功耗73 mW.     

一种采用4bit MDAC的12bit流水线模数转换器

采用GF 0.18μm标准CMOS工艺,设计并实现了一种12 bit 20 MS/s流水线模数转换器(ADC)。整体架构采用第一级4 bit与1.5 bit/级的相结合的方法。采用改进的增益数模单元(MDAC)结构和带驱动能力的栅自举开关来提高MDAC的线性度和精度。为了降低子ADC的功耗,采用开关电容式比较器。仿真结果表明,优化的带驱动的栅自举开关可减小采样保持电路(SHA)的负载压力,有效降低开关导通电阻,降低电路的非线性。测试结果表明:在20 MS/s的采样率下,输入信号为1.234 1 MHz时,该ADC的微分非线性(DNL)为+0.55LSB/-0.67LSB,积分非线性(INL)为+0.87LSB/-0.077LSB,信噪比(SNR)为73.21 dB,无杂散动态范围(SFDR)为69.72 dB,有效位数(ENOB)为11.01位。芯片面积为6.872 mm2,在3.3 V供电的情况下,功耗为115 mW。     

基于0.18μm CMOS工艺的 0.23pJ/step 11.05bit 有效位 125MS/s 流水线型模数转换器

本文描述了一款基于0.18μm标准CMOS工艺设计的12位 125-MS/s 的流水线型模数转换器。为了提高采样的线性度,采用了栅压自举开关和底极板采样技术。其微分非线性和积分非线性分别为0.79 LSB和0.86 LSB。在输入频率为10.5MHz时,本模数转换器可以实现11.05bit的有效位,在输入频率接近奈奎斯特频率时,仍可以达到10.5 bit的有效位。本模数转换器工作电压为1.9V,功耗62 mW,面积1.17 mm2,其中包含片内参考电压产生电路。本模数转换器的FOM值为0.23 pJ/step。     

一种用于红外读出电路的低温SAR ADC

本文提出了一种用于低温红外读出系统的连续逼近模数转换器（SAR ADC）电路。为了在很宽的温度范围内保证电路的性能,ADC中采用了一种温度补偿时域比较器结构。该比较器可在从室温到77K的极端工作温度条件下,实现稳定的性能和极低的功耗。该转换器采用标准的 0.35 μm CMOS 工艺制造,在77K的温度下,其最大微分非线性（DNL）和积分非线性（INL）分别为0.64LSB和0.59LSB。在采样率为200kS/s时可实现9.3bit的有效位数。在3.3V的电源电压下其功耗为0.23mW,占用的芯片面积为0.8*0.3 mm2。     

一种具有比较器失调后台校准的无采样保持放大器型14位100MS/s流水线模数转换器

本文实现了一种不具有前端采样保持放大器的14位100MS/s的流水线模数转换器。为了提高第一级采样网络的匹配性,本文提出了一种用于降低第一级子模数转换器的后台失调校准电路。后台失调校准电路保证了比较器总失调不超过内建冗余结构的校准范围。所提出的模数转换器采用0.18um CMOS工艺进行流片,面积为12mm2。在1.8V电源电压下,模数转换器功耗为237mW。测量结果显示,在100MHz采样频率、30.1MHz输入频率下,模数转换器的信号与噪声失真比（SNDR）为71dB,无杂散动态范围（SFDR）为85.4dB,最大微分非线性（DNL）为0.22LSB,最大积分非线性（INL）为1.4LSB。     

一种基于时间交织逐次逼近结构的高速低功耗ADC设计

本文介绍了一种采用28nm CMOS工艺实现的12位高速低功耗模数转换器。为了在低功耗的基础上实现高速模数转换,本设计选择时间交织结构为系统架构,单通道ADC采用逐次逼近结构。单通道SAR ADC采样速率90MS/s,4通道时间交织实现360MS/s的采样速率。测试结果表明,该ADC在360MS/s采样速率和33MHz输入信号频率下,测得的信噪失真比（SNDR）和无杂散动态范围（SFDR）分别为62.1dB和71.2dB,功耗为148mW。     

一个SFDR性能超过80dB的12-bit 40MS/s流水线模数转换器

摘要：本文介绍了一个以高无杂散动态范围(SFDR)和低功耗为优化目标,不需要校正的12-bit,40MS/s流水线模数转换器(ADC)。以4.9MHz正弦输入信号测试表明,本ADC微分非线性(DNL)的最大值为0.78LSB,积分非线性(INL)的最大值为1.32LSB,信噪失真比(SNDR)为66.32dB,SFDR为83.38dB。电路采用 0.18-um 1P6M CMOS工艺实现,整体芯片面积3.1mm×2.1mm,电源电压1.8V,功耗102mW。     

低功耗逐次逼近型模数转换器的设计

本文提出了一种低功耗逐次逼近型（Successive Approximation Register,SAR）模数转换器。电路采用MCS切换方式和二级全动态比较器以及可编程时钟产生电路,以实现低功耗的模数转换器。本设计基于SMIC 130 nm CMOS工艺,电源电压为3.3 V,采样速率为2 MS/s,仿真结果表明,ADC的SFDR为77.6 dB,SNDR为59.2 dB,其能达到9.55 bit分辨率,且功耗仅为0.198 mW。     

基于功耗优化的流水线ADC研制

提出了一种使流水线模数转换器功耗最优的系统划分方法。采用Matlab进行模拟,以信噪比(SNR)为约束,得出一定精度条件下,流水线ADC各子级分辨率和各级采样电容缩减因子的不同选取组合;又以功耗为约束,从以上多种组合中找到满足最低功耗的流水线ADC结构划分方法。基于以上分析,在SMIC 0.35μm工艺条件下,设计了一个10 bit、采样率20 MS/s的流水线ADC,并流片验证。2.1 MHz输入频率下测试,SFDR=73 dB、ENOB=9.18 bit,模拟部分核心功耗102.3 mW。     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.     

A 14-b 20-Msamples/s CMOS pipelined ADC

The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-μm CMOS occupies an area of 4.5×2.4 mm² and consumes 720 mW at 5 V     

An 8-bit 80-Msample/s pipelined analog-to-digital converter withbackground calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology     

A digital background calibration technique for time-interleavedanalog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm², and the power dissipation is 565 mW from a 5 V supply     

14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration

Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4 and 10.7 , respectively, compared to a 14 bit uncalibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18 um CMOS process occupies an active die area of 4.2 mm² and consumes 140 mW at 1.8 V and 50 MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69 to 0.39 LSB and from 33.60 to 2.76 LSB, respectively.     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...