共查询到19条相似文献,搜索用时 140 毫秒
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负偏压温度不稳定性效应(NBTI)已经成为影响CMOS集成电路可靠性的一个关键因素,而动态应力条件下的NBTI效应对器件和电路的影响越来越受到关注。对PMOSFET的动态NBTI效应进行了系统介绍,讨论了动态应力条件下NBTI(DNBTI)效应和静态应力下NBTI(SNBTI)退化机理,综述了DNBTI效应的动态恢复机制以及影响因素,最后介绍了NBTI效应对电路的影响。随着器件尺寸的日益缩小,如何提高电路的可靠性变得日益重要,进一步研究NBTI效应对电路的影响从而进行NBTI电路级可靠性设计已成为集成电路设计关注的焦点。 相似文献
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负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入SpectreTM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。 相似文献
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研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法 相似文献
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研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法. 相似文献
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负偏压温度不稳定性(NBTI)效应已成为影响数字电路设计的重要可靠性问题之一。首先讨论了PMOS晶体管中NBTI效应对数字电路的影响,提出针对不同工艺PMOS管中NBTI效应建模的流程,设计了一种基于SPICE模型的NBTI仿真模型。该模型能够通过Cadence软件调用,并在实际的数字电路设计中进行动态仿真,预测NBTI效应对电路性能的影响。基于该建模流程,在Cadence软件中对基于40 nm工艺的一级两输入与非门和四十级反相器组成的环形振荡器进行仿真。仿真结果表明,该模型能够对不同工艺下PMOS管中的NBTI效应进行准确、有效地仿真,为数字电路的可靠性设计提供保障。 相似文献
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《固体电子学研究与进展》2018,(1)
器件的负偏压温度不稳定性(Negative bias temperature instability,NBTI)退化依赖于栅氧化层中电场的大小和强反型时沟道空穴浓度,沟道掺杂浓度的不同显然会引起栅氧化层电场的变化。栅氧化层的厚度不仅影响栅氧化层电场,而且会影响沟道空穴浓度,因而,改变沟道掺杂浓度和栅氧化层厚度会引起NBTI退化的不同。首先利用pMOSFETS器件的能带图和NBTI的退化模型,推导出了器件NBTI随器件参数变化的公式,并修订了NBTI的数值模拟方法,然后分别利用理论计算和数值模拟的方法对不同器件参数、相同阈值电压的器件进行定量地计算和仿真,继而总结出一种分析器件NBTI退化的应用模型,可对集成电路和器件的可靠性设计提供指导。 相似文献
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当晶体管的特征尺寸减小到45 nm时,电路的可靠性已经成为影响系统设计一个关键性因素。负偏压温度不稳定性(NBTI)和泄露功耗引起的电路可靠性现象的主要原因,导致关键门的老化加重,关键路径延迟增加,最终使得芯片失效,影响系统的正常工作。为了缓解NBTI效应和泄露功耗对电路可靠性的影响,延长电路的使用寿命,文中提出了循环向量方法进行协同优化。在ISCAS85基准电路,利用本方法协同优化实验,NBTI效应平均延迟相对改善了10%,泄漏功耗平均降低了15%,证明了循环向量方法的可行性。 相似文献
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Jiann-Shiun Yuan Wen-Kuan Yeh Shuyu Chen Chia-Wei Hsu 《Microelectronics Reliability》2011,51(5):914-918
Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress. 相似文献
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Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB. 相似文献
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M. Houshmand Kaffashian R. Lotfi K. Mafinezhad H. Mahmoodi 《Microelectronics Journal》2011,42(12):1327-1334
Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit. 相似文献
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Jha N.K. Reddy P.S. Sharma D.K. Rao V.R. 《Electron Devices, IEEE Transactions on》2005,52(12):2609-2615
A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors. 相似文献
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Paulo F. Butzen Vinícius Dal Bem André I. Reis Renato P. Ribas 《Microelectronics Reliability》2010,50(9-11):1298-1303
Negative Bias Temperature Instability (NBTI) has become a critical reliability concern for nanometer PMOS transistors. A logic function can be designed by alternative transistor networks. This work evaluates the impact of the NBTI effect in the delay of CMOS gates considering both the effect of intra-cell pull-up structures and the effect of decomposing the function into multiple stages. Intra-cell pull-up PMOS transistor arrangements have been restructured to minimize the number of devices under severe NBTI degradation. Also, circuits decomposed into more than one stage have been compared to their single stage design version. Electrical simulation results reveal that the restructuring of intra-cell transistor networks recovers up to 15% of rise delay degradation due to NBTI, while the decomposition of single stage circuit topologies into multi-stage topologies tends to reduce the rise degradation delay at a cost of fall delay degradation. 相似文献
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Vijay Reddy Anand T. Krishnan Andrew Marshall John Rodriguez Sreedhar Natarajan Tim Rost Srikanth Krishnan 《Microelectronics Reliability》2005,45(1):31-38
We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases. 相似文献
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With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology. 相似文献
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s semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong system’s lifetime. Negative Bias Temperature Instability (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI analyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transistor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed. 相似文献