一种GPS软件接收机的频域粗同步算法研究

粗同步时间是衡量同步算法的重要指标之一,为了在较短的时间内完成粗同步,达到对导航信号的精同步的目的,在对时域粗同步算法工作机理深入研究的基础上,提出了一种GPS软件接收机的频域粗同步算法,并通过仿真得出在两种算法都能正确捕获导航信号的前提条件下,频域粗同步算法较时域粗同步算法同步时间短的结果,从而进一步验证了该算法的时效性、合理性,为今后开发GPS接收机应用平台提供了现实依据.     

WSN数据采集时间同步算法研究

针对现有的WSN时间同步算法不适用于数据采集时间同步的问题,以基于WSN的某洗煤厂设备点检系统电动机振动信号采集为例,提出了一种新的延时时间广播同步算法,详细分析了该算法的原理、在单跳WSN中的实现过程及其时间同步延时补偿和误差计算,并与其它WSN时间同步算法进行了比较,得出该算法开销小、能量消耗低、同步精度较高的结论。该算法的有效性在基于WSN的洗煤厂设备点检系统数据同步采集中已得到验证。     

无线传感器网络同步算法的研究与探讨

时间同步是无线传感器网络进行数据融合、TDMA调度、定位等基本应用的基础。从时间同步的概念和定义出发,首先对几种经典的常用的时间同步算法及新型的萤火虫同步和梯度同步算法进行了介绍,然后主要分析分布式的时隙互同步算法,最后展望了未来时间同步算法的研究方向。     

SAE AS6802协议研究及模块化仿真平台设计

分析安全关键领域的时间触发网络协议SAE AS6802与时间同步算法技术,分别对同步流程、时间同步角色、时序保持算法、集中控制算法、时钟纠正算法、同/异步派系检测算法以及通道择优方法等进行研究,归纳时间同步精度的影响因素。在此基础上,设计一种时间同步算法IP核,并构建基于SystemVerilog的模块化仿真验证平台。利用该平台对时间同步算法进行RTL级仿真,结果验证了该时间同步算法的正确性,其同步精度保持在亚微秒级,满足下一代高安全关键领域的应用要求。     

无线传感器网络按需时间同步算法研究

节点的时间同步是无线传感器网络的一项支撑技术。鉴于目前对低能耗的多跳时间同步算法的研究相对缺乏,本文在分析了TPSN时间同步算法的基础上,提出了一种适合低流量无线传感器网络的低能耗多跳按需时间同步算法。具体阐述了单点同步和多点同步算法,分析了算法的精度与复杂度。仿真实验表明本文提出的算法与TPSN算法相比,在相同精度的前提下,具有复杂度低、节能等优点。     

基于信息融合的分布式时间同步算法

时间同步算法作为无线传感器网络的支撑技术,成为近些年研究的一个热点。其中集中式时间同步算法一直以来被广泛研究,它依靠参考节点通过广播、泛洪或者多跳的方式达到全网时间同步,取得了良好的同步精度,但同时鲁棒性和可扩展性差。提出了一种分布式时间同步算法,通过融合全网节点的时间信息来达到时间同步,这种算法消除了网络拓扑变化和节点密度变化对集中式算法的影响。实验结果表明,针对典型的网络拓扑,分布式时间同步算法实现了全网时间同步,并且对于网络变化和节点数目变化具有鲁棒性。     

时钟同步算法的分析和比较

在许多分布式实时系统中.,要求整个分布式系统上的各个处理器时钟彼此同步,因而就要采取各种手段进行同步的处理。时钟同步算法保证了空间上分散的处理器时钟彼此同步。该文研究了当今基于软件实现的忍受故障的几种时钟同步算法:确定性、概率型和统计型同步算法并进行特性分析。本文提出了结构化分析的方法,有助于帮助分布式系统的设计者选择最合适的算法结构、系统硬件构成、故障模型、时钟同步质量等。     

无线传感器网络时间同步算法研究

时间同步技术是无线传感器网络中非常重要的协议之一,是保证传感器网络中各个节点协同工作的核心机制。根据有无参考节点将时间同步算法分为双向消息交换时间同步算法和分布式一致时间同步算法,其中双向消息同步机制广播消息交换算法和基于ACK帧的时间同步算法。这三类双向消息时间同步算法的时间同步消息发送数目逐级递减,能耗相对应降低;而分布式一致时间同步算法摒弃了参考节点的选择,同时同步所有的传感器节点,避免了参考节点失效而无法进行时钟同步的情况。基于现有研究的分析及归纳,最后给出了时间同步算法未来可能的研究方向。     

网络游戏引擎中同步技术研究综述*

由于网络游戏依托于现有的互联网技术,网络传输中的延迟、出错等问题总是不可避免的,因此游戏中状态的同步便是一个很大的问题。讨论了LockStep同步算法、Bucket同步算法、TimeWarp同步算法、基于DR的Bucket同步算法以及客户端预测等几种网络引擎同步技术,并在此基础上总结出在设计同步策略时应考虑的若干问题。     

选煤厂设备监测中时间同步算法研究

分析了适用于选煤厂设备采集的RBS时间同步算法,针对其建立同步时能耗较大和同步收敛时间较长的问题,提出了改进的RBS时间同步算法IRBS。利用无线通信能耗模型对IRBS算法和RBS算法进行了测试分析,测试结果表明,IRBS算法能明显减少同步过程中的能量消耗和同步收敛时间。     

A formal library of set relations and its application to synchronous languages

Set relations are particularly suitable for specifying the small-step operational semantics of synchronous languages. In this paper, a formal library of set relations for the definition, verification of properties, and execution of binary set relations is presented. The formal library consists of a set of theories written in the Prototype Verification System (PVS) that contains definitions and proofs of properties, such as determinism and compositionality, for synchronous relations. The paper also proposes a serialization procedure that enables the simulation of synchronous set relations via set rewriting systems. The library and the serialization procedure are illustrated with the rewriting logic semantics of the Plan Execution Interchange Language (PLEXIL), a rich synchronous plan execution language developed by NASA to support autonomous spacecraft operations.     

基于Java实现MobiLink同步

通过MobiLink,可使远程数据库和中心数据库保持同步,以达到数据共享。MobiLink的同步程序分为上传、下载与确认三个阶段,基于Java语言编写的同步脚本,能够有效地实现MobiLink的同步功能。文中介绍了MobiLink的特性、结构和同步原理及如何利用Java语言实现MobiLink同步。基于Java语言实现MobiLink的同步功能,在移动数据库系统中具有非常重要的现实意义。     

A formal semantics for debugging synchronous message passing-based concurrent programs

In this paper, we propose a semantic framework to debug synchronous message passing-based con- current programs, which are increasingly useful as parallel computing and distributed systems become more and more pervasive. We first design a concurrent programming language model to uniformly represent exist- ing concurrent programming languages. Compared to sequential programming languages, this model contains communication statements, i.e., sending and receiving statements, and a concurrent structure to represent com- munication and concurrency. We then propose a debugging process consisting of a tracing and a locating procedure. The tracing procedure re-executes a program with a failed test case and uses specially designed data structures to collect useful execution information for locating bugs. We provide for the tracing procedure a struc- tural operational semantics to represent synchronous communication and concurrency. The locating procedure backward locates the ill-designed statement by using information obtained in the tracing procedure, generates a fix equation, and tries to fix the bug by solving the fix equation. We also propose a structural operational semantics for the locating procedure. We supply two examples to test our proposed operational semantics.     

Estimation of synchronous machine parameters by standstill tests

In this paper we present the results of a time-domain identification procedure to estimate the linear parameters of a salient-pole synchronous machine at standstill.A new approach is proposed for the estimation of synchronous machine coupled to DC-chopper and Pseudo Random Binary Sequences excitations; using data recorded during steady-state operation of the chopper-machine unit. This procedure consists of defining and conducting the standstill tests, identifying the model structure, estimating the corresponding parameters, and validating the resulting model. The signals used for identification are the different excitation voltages at standstill and the flowing current in different windings. We estimate the parameters of operational impedances, or in other terms, the reactances and the time constants.The results are presented from tests on a synchronous machine of 3 kVA/220 V/1500 rpm.     

Designing self-timed devices using the finite automaton model

The authors suggest a procedure for designing a self-timed device defined by the finite automaton model. This procedure proves useful when designing these devices using the available synchronous behavior specifications. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgement delay counter     

Numerical determination of reduced order linear synchronous machine models

A method is presented for the determination of reduced order linear synchronous machine models for dynamic stability evaluation's and as a basis for excitation and governor controller design. The reduction technique is based on Davisons method and is presented in such a way that enables it to be used in isolation, for general linear model reduction, or to be included in an overall synchronous machine stability procedure.     

基于T.120的协同GIS研究

首次把CoGIS分同步CoGIS和异步CoGIS两类，进一步阐述体系结构、功能模块，提出基于T．120数据会议系统的CoGIS原型，并详细分析了原型的层次结构和同步流程。进一步丰富了CoGIS的外廷和内涵，井为CoGIS系统的实现提供了切实可行的方案。     

多路视频同步记录与回放系统

针对当前军事导调系统只能实时播放任务图像画面, 无法完成各类图像数据的同步记录与回放、场景不能自动按时序切换等问题, 采用多路视频同步记录、同步回放、流程自动控制等技术, 构建了多路视频同步记录与回放系统, 该系统可随时再现军事训练任务中多台投影机实时显示内容, 解决了军事作战模拟训练中指挥员无法事后分析演练全过程的难题. 实际应用表明该技术有效提升了军事作战模拟训练效能, 具有重要的现实和军事意义.     

Performance Enhancement for Rigid Tapping by Iterative Learning Control

In this study, an iterative learning control (ILC) algorithm is proposed to improve synchronous errors in rigid tapping. In rigid tapping, the displacements of the z‐axis and spindle must be kept synchronous to prevent damage. Using learning control provides better commands for both the z‐axis and spindle dynamics, improving the synchronicity of the output responses of the z‐axis and spindle. The proposed ILC makes use of synchronous errors in the previous cycle of tapping to modify the current position commands of both the z‐axis and spindle. A systematic algorithm is proposed for the computation of learning gains that guarantee the monotonic convergence of synchronous errors. A systematic procedure of applying ILC to rigid tapping is also proposed, where the ideas of effective learning gains and stop learning criteria are discussed. Experimental results on a tapping machine verify the effectiveness of the proposed ILC algorithm.     

The Saga of Synchronous Bus Arbiter: On Model Checking Quantitative Timing Properties of Synchronous Programs

Quantified Discrete-time Duration Calculus, (QDDC), is a form of interval temporal logic [14]. It is well suited to specify quantitative timing properties of synchronous systems. An automata theoretic decision procedure for QDDC allows converting a QDDC formula into a finite state automaton recognising precisely the models of the formula. The automaton can be used as a synchronous observer for model checking the property of a synchronous program. This theory has been implemented into a tool called DCVALID which permits model checking QDDC properties of synchronous programs written in Esterel, Verilog and SMV notations.In this paper, we consider two well-known synchronous bus arbiter circuits (programs) from the literature. We specify some complex quantitative properties of these arbiters, including their response time and loss time, using QDDC. We show how the tool DCVALID can be used to effectively model check these properties (with some surprising results).