长线网预处理的过点分配算法

提出了一个长线网预处理的过点分配算法.该算法不仅考虑了过点和物理连接端的连接费用、总体布线单元边界上不同过点之间的互斥费用,而且考虑了同一线网不同过点之间的错位费用.实验结果表明,该算法极大地提高了详细布线阶段的布线质量和速度,特别是对于长线网而言,效果更为显著.     

基于线网类型分析的过点分配算法

过点分配是布线过程中位于总体布线和详细布线之间的一个步骤，它用于在详细布线之前确定线网在总体布线单元边界上的物理位置．本文提出一种新的过点分配的启发式算法，它基于总体布线后的线网类型的分析，考虑了总体布线单元中障碍对过点分配的影响，把整个布线区域的过点分配问题转化成一系列的单列（行）总体布线单元边界的过点分配问题，然后利用经典的线性分配方法进行过点的分配．     

Full-Chip Scalable Routing Framework Considering Congestion and Performance

提出一个全新的全芯片可控布线系统框架,同时考虑布线拥挤度和芯片性能.为了在总体布线和详细布线之间架起桥梁,该框架把总体布线和详细布线集成起来,交互进行,每完成一个线网的布线,都及时对布线资源进行更新,由此可以得到精确的资源估计结果,有利于指导后续总体布线决策.该系统框架的主要特征包括快速的基于模式的和基于外框约束下最短路算法的总体布线器、基于迷宫算法的拥挤度驱动的详细布线器以及在两个布线器之间很好的交互性.在该布线系统框架中,为了优化电路性能,在布线中关键线网被赋予更高的优先级.同时,为了优化不同的布线目标,可以采用不同的线网排序策略.该布线系统框架在一套公用的测试电路上完成测试,并与之前提出的多级布线系统框架进行比较,实验结果表明,文中提出的布线系统框架在电路性能、布通率和运行时间方面都取得了很大改进.     

考虑拥挤度和性能的全芯片可控布线系统框架

提出一个全新的全芯片可控布线系统框架,同时考虑布线拥挤度和芯片性能.为了在总体布线和详细布线之间架起桥梁,该框架把总体布线和详细布线集成起来,交互进行,每完成一个线网的布线,都及时对布线资源进行更新,由此可以得到精确的资源估计结果,有利于指导后续总体布线决策.该系统框架的主要特征包括快速的基于模式的和基于外框约束下最短路算法的总体布线器、基于迷宫算法的拥挤度驱动的详细布线器以及在两个布线器之间很好的交互性.在该布线系统框架中,为了优化电路性能,在布线中关键线网被赋予更高的优先级.同时,为了优化不同的布线目标,可以采用不同的线网排序策略.该布线系统框架在一套公用的测试电路上完成测试,并与之前提出的多级布线系统框架进行比较,实验结果表明,文中提出的布线系统框架在电路性能、布通率和运行时间方面都取得了很大改进.     

一种新的基于知识的四边通道布线算法

本文提出了一种新的基于知识的双层四边通道布线算法,该算法对四边通道的布线是通过以下四步完成的。首先,对四边通道的四个角布线,其次,对关键线网优先布线,接下来,利用线网间相互制约关系进行同步增长布线;最后,对仍然没有完成连接的线网,用李氏算法布线。由于使用了启发式规则,使得该算法具有较高的布通率和布线效率。     

考虑光学邻近效应的详细布线算法

提出了一种考虑光学邻近效应的详细布线算法.该算法在布线过程中,充分考虑了线网走线相对位置及布线线形对其光学邻近效应的影响,通过相应的光刻模拟模型定义了用于估计光学邻近效应(optical proximity effect,OPE)的OPE费用函数,并采用OPE费用阈值控制Steiner树的生长方向和走线路径的选择,同时兼顾线网长度.为提高算法效率,避免布线过程中反复调用光学模拟程序带来的算法运行速度慢的问题,对可能的走线模式建立了计算OPE费用所需的光强查找表格,使算法的运行速度大大提高.在实际的工业用例上的实验结果表明,本文所提出的详细布线算法使布线结果中的OPE问题得到很大程度的改善,有利于后处理过程中的光学邻近效应校正技术的运用,算法的运行时间是可以接受的.     

考虑光学邻近效应的详细布线算法

提出了一种考虑光学邻近效应的详细布线算法.该算法在布线过程中,充分考虑了线网走线相对位置及布线线形对其光学邻近效应的影响,通过相应的光刻模拟模型定义了用于估计光学邻近效应(optical proximity effect,OPE)的OPE费用函数,并采用OPE费用阈值控制Steiner树的生长方向和走线路径的选择,同时兼顾线网长度.为提高算法效率,避免布线过程中反复调用光学模拟程序带来的算法运行速度慢的问题,对可能的走线模式建立了计算OPE费用所需的光强查找表格,使算法的运行速度大大提高.在实际的工业用例上的实验结果表明,本文所提出的详细布线算法使布线结果中的OPE问题得到很大程度的改善,有利于后处理过程中的光学邻近效应校正技术的运用,算法的运行时间是可以接受的.     

动态串扰优化的开关盒布线

针对超深亚微米芯片设计中的开关盒布线问题提出了可变参数的串扰优化布线算法.该算法充分利用了双层布线资源,将动态信号波形和耦合电容结合起来考虑,进一步减小了线网间的总串扰,并力求通孔数最少.实验证明,本算法能够获得更加优化的布线方案.     

一个基于层次式PB角钩链结构的区域布线器

提出一个新的基于层次式PB角钩链结构的多层无网格布线器.该布线器基于PB层次式角勾链数据结构和网块扩展算法,使用朝向目标的加速策略提高算法的运行速度,并使用改进的二叉区间树管理算法的中间数据.还提出了基于拥挤度的无网格拆线重布算法.通过显式记录每个线网段周边的拥挤状况,并将其结合到网块扩展的费用当中,使拆除线网的选择和待布线网的路径搜索统一起来.实验结果表明,该布线器能有效地提高布通率,且算法运行速度较快.     

一个基于层次式PB角钩链结构的区域布线器

提出一个新的基于层次式 PB角钩链结构的多层无网格布线器 .该布线器基于 PB层次式角勾链数据结构和网块扩展算法 ,使用朝向目标的加速策略提高算法的运行速度 ,并使用改进的二叉区间树管理算法的中间数据 .还提出了基于拥挤度的无网格拆线重布算法 .通过显式记录每个线网段周边的拥挤状况 ,并将其结合到网块扩展的费用当中 ,使拆除线网的选择和待布线网的路径搜索统一起来 .实验结果表明 ,该布线器能有效地提高布通率 ,且算法运行速度较快     

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem

Routing is one of the important steps in very/ultra large-scale integration (VLSI/ULSI) physical design. Rectilinear Steiner minimal tree (RSMT) construction is an essential part of routing. Macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase. Obstacle-avoiding RSMT (OARSMT) algorithms are useful for practical routing applications. However, OARSMT algorithms for multi-terminal net routing still cannot meet the requirements of practical applications. This paper focuses on the OARSMT problem and gives a solution to full-scale nets based on two algorithms, namely An-OARSMan and FORSTer. (1) Based on ant colony optimization (ACO), An-OARSMan can be used for common scale nets with less than 100 terminals in a circuit. An heuristic, greedy obstacle penalty distance (OP-distance), is used in the algorithm and performed on the track graph. (2) FORSTer is a three-step heuristic used for large-scale nets with more than 100 terminals in a circuit. In Step 1, it first partitions all terminals into some subsets in the presence of obstacles. In Step 2, it then connects terminals in each connected graph with one or more trees, respectively. In Step 3, it finally connects the forest consisting of trees constructed in Step 2 into a complete Steiner tree spanning all terminals while avoiding all obstacles. (3) These two graph-based algorithms have been implemented and tested on different kinds of cases. Experimental results show that An-OARSMan can handle both convex and concave polygon obstacles with short wire length. It achieves the optimal solution in the cases with no more than seven terminals. The experimental results also show that FORSTer has short running time, which is suitable for routing large-scale nets among obstacles, even for routing a net with one thousand terminals in the presence of 100 rectangular obstacles.     

Routing on field-programmable switch matrices

In this paper, we address the problem of routing nets on field programmable gate arrays (FPGAs) interconnected by a switch matrix. We extend the switch matrix architecture proposed by Zhu et al. (1993) to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within a two-dimensional switch matrix, this problem examines the issue of how to route a given net traffic through the switch matrix structure. First, we define the problem as a general undirected graph in which each vertex has one single color among six possible colors and formulate it as a constraint satisfaction problem. This is further modeled as a 0-1 multidimensional knapsack problem for which a fast approximate solution is applied. Experimental results show that the accuracy of our proposed heuristic is quite high for moderately large switch matrices.     

基于自由分层的通道区布线算法

本文在分析线网之间关系的基础上提出了自由分层条件下的通道区布线模型:同层限制图Gs,相交图Gi,基于这一模型,分析了二层布线条件下对线网分层和布线序的基本限制,导出了分层的基本原则,在此基础上,分析了线网可Overlap的性质和条件,从总体分析的思想出发,提出了直接以完成布线通道区所需面积最小化为目标的分层布线算法,实验结果表明,通道区布线面积和通孔的致目比基于横竖分层的布线算法有较大减少,对于Deutsch′s diffjcult example,该算法获得18个track解。     

Automatic synthesis of FPGA channel architecture for routabilityand performance

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A channel architecture synthesis algorithm based on simulated annealing has been developed which enhances channel routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance. Excellent results have been obtained for a set of benchmark examples and industrial designs     

Architecture driven circuit partitioning

In this paper, we propose an architecture driven partitioning algorithm for netlists with multiterminal nets. Our target architecture is a multifield-programmable gate array (FPGA) emulation system with folded-Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize routability. To that end, we introduce a new cost function: the average number of pseudoterminals per net in a multiway cut. Experimental result shows that our algorithm is very effective in terms of the number of chips used and routability as compared to other methods     

LSI版图设计中的一种P／G网布线法

本文提出了一种有效的P/G网布线算法和在积木块式布图系统中实现的策略。与以往算法比较,此算法允许每条电源网具有多个馈电脚存在。其策略包括四个部分:(1)一种有效的层次式自上而下的P/G网平面性分析和拓扑路径分配算法;(2)P/G网线宽的确定;(3)总体压缩和再布线后P/G网布线信息的动态修改;(4)与信号网一起的平面性无网格电源网通道详细嵌入。实验结果表明我们的P/G网布线方法可获得令人满意的布线结果。     

一种带权动态调整的总体布线算法及其实现

本文对现有的总体布线方法及宏单元阵列总体布线问题进行了详细分析,提出了一种基于带权动态调整思想的适合于宏单元阵列一层半和双层版图模式的总体布线算法,其目标是合理地利用已确定的布线区域,使各线网均匀地分布在芯片上,获得尽可能高的布通率。     

超平面布线

本文大胆打破了传统通道模型的束缚,建立了一个能更好体现多层布线内在本质约束的新模型：超平面布图模型,在该模型下提出了超平面布线算法。该算法以全新的逆向删冗策略成功地解决了布线线序的问题,使线网布线真正达到了并行处理。算法遵循了王守觉先生关于总体分析的方法作为解决超平面布线问题的指导思想,以布线层数最少化和通孔最少化为目标,通过动态地分析线网间的相互位置关系,全局考虑去释放各线网占据的不合理布线资源     

Congestion estimation for 3-D circuit architectures

Three-dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks.