A high f/sub OSC//f/sub T/ ratio VCO in SiGe BiCMOS technology

A 37-GHz voltage controlled oscillator (VCO) fabricated in IBM's 47-GHz SiGe BiCMOS technology is presented. The VCO achieves a phase noise of -81dBc/Hz at 1-MHz offset from the carrier while delivering an output power of -30dBm to 50 /spl Omega/ buffers. Drawing 15-mA of dc current from a 3-V power supply the VCO occupies 350/spl mu/m/spl times/280/spl mu/m of silicon area. Capacitive emitter degeneration and compact layout are used to achieve high f/sub OSC//f/sub T/ ratio.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.     

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB

A technique to enhance the linearity of continuous-time operational transconductance amplifiers (OTA)-C filters working at high frequencies is proposed. Each OTA consumes 10.5 mW and the transconductance can be tuned from 70 to 160 /spl mu/A/V while the IM3 remains below -70 dB up to 50 MHz for a 1.3-V/sub pp/ differential input. For a 20-MHz low-pass second-order filter implementation, the measured IM3 with an input voltage of 1.3 V/sub pp/ is below - 65 dB. The supply voltage is 3.3 V. Experimental results of the circuit, fabricated in a standard CMOS 0.35-/spl mu/m technology, are presented.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

A high-speed 850-nm optical receiver front-end in 0.18-/spl mu/m CMOS

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-/spl mu/m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3/spl middot/10/sup -10/. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called "f/sub T/ doublers" are used. For a differential 10 mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV/sub pp/ input signal results in a bit error rate of 7/spl middot/10/sup -14/. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems

A fully differential 40-Gb/s electro-absorption modulator driver is presented. Based on a distributed limiting architecture, the circuit can supply up to 3.0-V/sub pp/ (peak-to-peak) per side in a 50-/spl Omega/ load at data rates as high as 44 Gb/s. Both the input and the output are internally matched to 50 /spl Omega/ and exhibit return loss of better than 10 dB up to 50 GHz. Additional features of the driver include the use of a single -5.2-V supply, output swing control (1.7-3.0-V/sub pp/ per side), dc output offset control (-0.15 V to -1.1 V), and pulsewidth control (30% to 66%). The driver architecture was optimized based on a comprehensive analytical derivation of the frequency response of cascaded source-coupled field-effect transistor logic blocks using both single and double source-follower topologies.     

A matrix amplifier in 0.18-/spl mu/m SOI CMOS

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 /spl Omega/ using m-derived half sections; the measured S/sub 11/ and S/sub 22/ values exceed -7 and -12 dB, respectively. Integrated in 2.0/spl times/2.9mm/sup 2/, it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies.     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

5.8-GHz circularly polarized rectifying antenna for wireless microwave power transmission

This paper reports a new circularly polarized (CP) high-gain high-efficiency rectifying antenna (rectenna). The CP rectenna can be rotated and still maintain a constant dc output voltage. The high-gain antenna has an advantage of reducing the total number of rectenna elements to cover a fixed area. The rectenna is etched on Rogers Duroid 5870 substrate with /spl epsi//sub r/=2.33 and 10 mil thickness. A high-gain dual-rhombic-loop antenna and a reflecting plane are used to achieve a CP antenna gain of 10.7 dB and a 2:1 voltage standing-wave ratio bandwidth of 10%. The rectenna's pattern has an elliptical cross section with orthogonal beamwidths of 40/spl deg/ and 60/spl deg/. The rectenna circuit has a coplanar stripline band-reject filter that suppresses the re-radiated harmonics by 20 dB. A highly efficient Schottky diode is used for RF-to-dc conversion with an efficiency of approximately 80% for an input power level of 100 mW and a load resistance of 250 /spl Omega/.     

Novel FRESURF LDMOSFET devices with improved BV/sub dss/-R/sub dson/

In this letter, we propose and demonstrate a novel device based on a floating reduced surface field (FRESURF) concept which allows the realization of significantly higher breakdown voltage in a thin epitaxy-based power IC technology. The newly proposed device with the floating buried layer pulled back from the source side is able to realize an enhanced breakdown voltage (BV/sub dss/) without degrading the specific on-resistance (R/sub dson/A). BV/sub dss/-R/sub dson/A values like 47 V-0.28 m/spl Omega//spl middot/cm/sup 2/ or 93 V-0.82 m/spl Omega//spl middot/cm/sup 2/ have been realized with a conventional power IC technology without any added process complexity.     

High-gain SiGe transimpedance amplifier array for a 12/spl times/10 Gb/s parallel optical-fiber link

A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 /spl mu/A/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12/spl times/10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools.     

12 W/mm AlGaN-GaN HFETs on silicon substrates

Al/sub 0.26/Ga/sub 0.74/N-GaN heterojunction field-effect transistors were grown by metal-organic chemical vapor deposition on high-resistivity 100-mm Si (111) substrates. Van der Pauw sheet resistance of the two-dimensional electron gas was 300 /spl Omega//square with a standard deviation of 10 /spl Omega//square. Maximum drain current density of /spl sim/1 A/mm was achieved with a three-terminal breakdown voltage of /spl sim/200 V. The cutoff frequency and maximum frequency of oscillation were 18 and 31 GHz, respectively, for 0.7-/spl mu/m gate-length devices. When biased at 50 V, a 2.14-GHz continuous wave power density of 12 W/mm was achieved with associated large-signal gain of 15.3 dB and a power-added efficiency of 52.7%. This is the highest power density ever reported from a GaN-based device grown on a silicon substrate, and is competitive with the best results obtained from conventional device designs on any substrate.     

A bipolar monolithic multigigabit/s decision circuit

A monolithic multigigabit/s decision circuit using a 0.5-/spl mu/m bipolar process technology called advanced super self-aligned technology (SST-1A) has been developed. A special decision circuit including a novel current switch based on a nonthreshold logic circuit and a cutoff prevention principle was designed and fabricated. An output voltage swing of 1 V across a 50-/spl Omega/ load, a fast transition time of 90 ps (10-90%) and 3.6 Gbit/s operation have been achieved. Power dissipation per chip is about 600 mW. This IC is applicable to very-high-speed optical fiber transmission system repeaters.     

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.     

High-power (200 mW) singlemode operation of InGaAsN/GaAs ridge waveguide lasers with wavelength around 1.3 /spl mu/m

High-power narrow ridge waveguide lasers emitting with a wavelength around 1.3 /spl mu/m were realised with a single In/sub 0.36/GaAsN/sub 0.022/ quantum well with GaAs barriers. A narrow vertical far-field angle of 35/spl deg/ was obtained. Single lateral mode continuous-wave operation with slope efficiency of 0.57 W/A, series resistance of 2.6 /spl Omega/, and kink-free output power of 210 mW was achieved.     

CMOS wideband amplifiers using multiple inductive-series peaking technique

This work presents the technique of multiple inductive-series peaking to mitigate the deteriorated parasitic capacitance in CMOS technology. Employing multiple inductive-series peaking technique, a 10-Gb/s optical transimpedance amplifier (TIA) has been implemented in a 0.18-/spl mu/m CMOS process. The 10-Gb/s optical CMOS TIA, which accommodates a PD capacitor of 250 fF, achieves the gain of 61 dB/spl Omega/ and 3-dB frequency of 7.2 GHz. The noise measurement shows the average noise current of 8.2 pA//spl radic/Hz with power consumption of 70 mW.