一种不规则2DMesh的NoC路由算法

NoC的网络拓扑结构是其研究的重要方面,在一些实际应用中,NoC系统通常集成多个不同功能、不同尺寸、不同通讯需求的组件,而规则的拓扑结构并不适应于在这种类型的NoC中应用,因此不规则Mesh网络被应用于不规则的NoC系统,为解决规则Mesh路由算法在不规则Mesh中无法保证路由连通性问题。提出一种不规则Mesh无死锁路由算法,同时此算法与其他算法相比,具有更少的虚通道和更优秀的路由路径选择。     

不规则网络拓扑结构下的多棵树路由算法研究

为了提高不规则网络拓扑结构的路由效率,提出了一种新型路由算法-多棵树路由算法.考虑了原始路由算法的不足,平均了网络中各个通道的利用率,降低路由表的平均路径长度,同时在死锁发生时能够及时有效的进行死锁恢复,解决了先前路由算法中通道负载集中、通道利用率低、路由表平均路径长度过长的问题.通过模拟真实硬件环境的模拟器软件,表明了在不同规模、不同负载下的不规则网络下多棵树路由算法具有更高的效率.     

基于3D Mesh结构的一种静态路由算法

3D NoC在同构多核系统中相比2D NoC具有更为优越的性能.本文在研究3D Mesh结构的基础上,对拓扑结构中的平均延时和理想吞吐量进行了理论上的评估,并提出了一种基于3D Mesh的新的静态路由算法,最后运用NS2网络仿真软件对其进行仿真和比较.实验结果显示,新的路由算法可以有效地提高吞吐量,并在大规模数据传输时...     

Mesh网络耐故障虫孔路由

耐故障是互连网络设计中的一个重要问题。本文提出了一种新的耐故障路由算法,并将其应用于使用虫孔交换技术的Mesh网络。由于使用了较低的路由限制,这一算法具有很强的自适应性,可以在各种不同故障域的Mesh网络中保持路由的连通性和无死锁性;由于使用了最小限度的虚拟通道,这一算法所需的缓冲器资源很少,非常适宜构建低成本的耐故障互连网络;由于根据本地故障信息进行绕行故障节点的决策,这一算法的路由决策速度较快并且易于在互连网络中实现。最后网络仿真试验显示,这一算法具有良好的平滑降级使用的性能。     

基于2D Mesh的NoC路由算法设计与仿真

在研究Turn Model模型的基础上,提出一种基于2D Mesh结构的XY-YX路由算法,是一种确定性的无死锁的最短路径路由算法。给出无死锁的证明,通过片上网络（NoC）模拟仿真实验平台NIRGAM,将该算法在一个4×4的2D Mesh网络中进行仿真,并与XY路由算     

PRDT（2，1）架构的NoC系统容错路由算法

链路和节点的故障会导致网络中许多节点无法相互通讯,因此容错性是NoC系统设计中的一个重要问题。基于一种新的NoC网络拓扑结构PRDT（2,1）,提出一种PRDT（2,1）容错路由算法以及相应的节点失效算法。节点失效算法通过使较少数量的无故障节点失效来构造矩形故障区域,PRDT（2,1）容错路由算法仅使用了最小数量的虚拟通道并提供足够的自适应性以实现无死锁容错路由。只要故障区域没有断开网络,这一算法能够保证路由的连通性。算法在不同故障率的PRDT（2,1）网络中仿真,结果显示这一算法具有良好的平滑降级使用特性。     

基于无线Mesh网络的煤矿应急救援系统设计研究

针对煤矿井下巷道特点,指出煤矿井下无线Mesh网络适于组建链状网络拓扑结构,并应结合巷道具体环境进行电磁波衰减理论分析和节点间距设计;针对现有的路由协议不能满足煤矿井下无线Mesh网络链状拓扑结构的要求,结合MIC判据,提出了一种反应式路由协议与先验式路由协议相结合的方法;在此基础上,给出了基于无线Mesh网络的煤矿应急救援系统的整体结构及特点。实验结果表明,把无线Mesh网络应用到煤矿应急救援系统中,提高了救灾工作的安全性、可靠性及灵活性。     

Mesh网中高效无死锁自适应路由算法

提出了一种新的应用于三维Mesh网中的无死锁路由算法.在当今的商用多计算机系统中,二维和三维的Mesh网是多处理器网络最为常用的拓扑结构之一.在应用于Mesh网的平面自适应路由(Planar Adaptive Routing)算法中,每条物理通道只需三条虚拟通道就可以有效地在三维以及更高维的Mesh网中避免死锁的产生.然而,采用该算法,网络拓扑一维和三维分别有两条和一条虚拟通道始终处于空闲状态.该文所提出的算法针对三维Mesh网,每条物理通道只需两条虚拟通道就可以有效地避免死锁.文中通过充分的模拟数据验证了此算法的有效性.     

基于PRDT的16节点NoC路由算法

网络结构对于片上网络系统的性能和功耗发挥着重要作用，PRDT(2,1)有着较低的网络直径和平均距离、常数的节点度以及良好的可扩展性，这些特点使其非常适于NoC。为了提高小规模PRDT的路由性能，该文提出了一种binary路由算法，当网络规模不大于16时，该算法无须使用虚拟通道即可实现无死锁路由，通过增加少量虚拟通道，可改进为完全自适应路由算法。对所提出的路由算法与原有的向量路由算法进行仿真比较，结果显示binary算法在硬件成本较低的同时，性能更为优异，完全可以应用于基于PRDT的小规模NoC网络。     

不规则网络中基于拐弯模型的路由算法的设计

由虫孔路由交换器连接而成的不规则拓扑网络，越来越多地用于构建工作站机群系统（NOWs），以实现高性能价格比的并行处理．采用虫孔路由技术，网络中容易发生死锁．交换器之间连接的不规则性，使路由避免死锁问题变得更加复杂．本文给出了在不规则网络中，设计基于拐弯模型的无死锁路由算法的一般方法，并采用扩展链路方向的方法得到多种路由策略，确定了up-first与down-last两种性能较优的路由算法．最后通过模拟实验，评价了算法的性能．     

Exploiting and evaluating the potentials of the link addition method for NoC transient error mitigation

Transient errors in a Network on Chip (NoC) result in some problems such as network blockage, packets loss or incorrect delivery, which would decrease the network throughput and degrade the successful delivery rate. Many fault tolerant mechanisms, such as error correcting code, retransmission and redundancy for the NoC, have been proposed to mitigate transient errors and guarantee the communication quality. Different from these existing methods, the paper aims at exploiting the potentials of the link addition strategy for transient error alleviation. The regular link addition as well as the customized link addition based on Mesh is designed for alleviating NoC transient errors. The regular design is suitable for the general purpose case while the partially customized design exploits the inherent communication characteristics and the reliability requirement of applications for some specified cases. The experimental results for typical network benchmarks confirm that the proposed link addition methods are effective to improve NoC performance and reliability. (1) In the case of the regular link addition, 4 × 4 Torus brings the throughput to increase by 45.76% and 87.34% over Mesh for the transpose traffic and the uniform traffic respectively. The reliability metrics of Torus over Mesh are up to 56.65% and 12.71% for the transpose traffic and the uniform traffic respectively. (2) The novel customized reliability-aware link addition mechanism makes the throughput improvement up to 17.4%, 53.5% and the reliability metric up to 16.34%, 57.76% over standard Mesh for the transpose traffic and the hotspot traffic respectively. In addition, the area overhead and power consumption of NoCs are also evaluated by the tool—Orion in the paper.     

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology cannot ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.     

基于FPGA的NoC硬件系统设计

设计了基于FPGA的片上网络系统硬件平台。系统由大容量的FPGA、存储器、高速A/D与D/A、通信接口和一个扩展的ARM9系统组成。完成了集高速数字信号处理、视频编解码和网络传输功能与一体的多核系统设计。针对典型的3×3 2D Mesh结构的NoC系统应用进行了探讨,阐述了NoC系统设计过程中的关键技术,并使用SigXplorer软件对系统的信号完整性解决方案进行了PCB的反射与串扰仿真。     

Action-Level Real-Time Network-on-Chip Modeling

To simulate time-constrained operations and scheduling for Network-on-Chip (NoC) systems, we introduce a new set of component specifications at flit level grounded in Action-Level Real-Time DEVS formalism. These models capture the dynamics of NoC systems through action-based behavior under strict execution time intervals. These DEVS-based models are well-suited for development and simulation of asynchronous NoC architectures. This is achieved by extending the DEVS-Suite simulator to support real-time executions of ALRT-DEVS models. Representative simulation models capturing structure and behavior of prototypical Mesh NoC systems are developed. A set of experiments are designed, implemented, executed, and analyzed to show the kind of real-time simulation capabilities that can be achieved for Network-on-Chip systems.     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.     

基于Rent规则的片上网络局部化特性流量生成算法

针对传统片上网络(NoC)流量模型的空间分布不符合实际应用中通信局部化特性、网络带宽开销大的问题,提出一种基于Rent规则的NoC局部化特性流量生成算法。该算法通过建立有限Mesh结构的通信概率分布模型,并利用通信概率矩阵对各节点匀速发包获得合成流量,实现通信局部化。实验模拟了不同局部化程度、不同网络尺寸的合成流量;仿真结果表明,与Random Uniform、Bit Complement、Reversal、Transpose、Butterfly等5种传统合成流量相比,该算法合成流量的局部化程特性更好、网络带宽开销更低,接近实际通信流量。     

基于拥塞控制的片上网络多播路由算法

为了满足片上网络日益丰富的应用要求,多播路由机制被应用到片上网络,以弥补传统单播通信方式的不足。以Mesh和Torus类的片上网络为例,分析了基于路径的3种多播路由算法(即XY路由、UpDown路由和SubPartition路由算法),并研究了相应的拥塞控制策略。通过模拟实验表明,多播较单播通信具有更小的平均传输延时和更高的网络吞吐量,且负载分配均匀;特别是SubPartition路由算法随着规模增大效果更加明显;提出的多播拥塞控制机制,能更有效地利用多播通信,提高片上网络的性能。