三维微波集成电路的发展

近几年来,三维微波集成电路的研制在各方面均取得了一定的进展,作为新一代体积更小的微波集成电路,必将随着信息时代的发展,在移动通信、卫星直播电视等装置中获得广泛应用。本文综述三维微波集成电路近几年来的发展。     

微波集成电路技术—回顾与展望

半个多世纪来 ,微波电路技术经历了从分立电路、两维微波集成电路、三维微波集成电路等阶段。在回顾这一发展历程后 ,介绍多层微波集成电路和三维微波集成电路。阐述其产生背景、关键技术及发展方向。文中将涉及微加工技术以及从直流至射频的多芯片全集成新概念。瞻望二十一世纪前景。     

Si基微波单片集成电路的发展

随着半导体制造技术和材料技术的进步,Si基微波单片集成电路逐渐向高频、高线性、低噪声、低成本方向发展。介绍了近年国内外在Si基微波单片集成电路在制造工艺、电路结构和制作材料上的革新,阐述了三维Si微波单片集成电路技术、隔离槽技术、Si高阻衬底技术、SiGe技术等对Si基微波单片集成电路发展的影响,并列举了一些典型的应用。最后展望了Si基微波单片集成电路的发展前景。     

微电子组(封)装技术的新发展

微组装技术的基础是SMT,实现了IC器件封装和板级电路组装这两个电路组装阶层之间技术上的融合,其发展方向是器件封装、组装与SMT自动化设备的紧密结合。微电子封装技术的基础是集成电路IC封装技术,发展方向是三维立体封装技术和微机电封装技术。重点论述了三维(3D)立体封装技术的最新发展,并介绍IC集成电路制造技术虚拟培训系统。     

一种与VLSI技术兼容的新型三维集成射频干扰滤波器

基于双π型电磁干扰滤波器(EMIF)的电路结构，借鉴集成电路超微细加工技术，提出了与等平面超大规模集成电路工艺完全兼容的一种新型三维集成射频干扰滤波器电路；简要介绍了该电路的绝缘层上金属薄膜三维集成制造方法，建立了电路传递函数模型，并进行了简要分析。该电路可用于制作适合未来电子系统高频化、小型化、轻型化和片式化信号处理的RF片上系统。     

二维和三维集成电路的热阻计算

聚焦芯片功耗密度、水平互连焦耳热和垂直互连焦耳热三种温升因素，构造二维和三维集成电路的热阻分析模型，基于2003年国际半导体技术发展路线图（2003-ITRS），计算二维和三维集成电路的热阻和温升参数，给出热阻二维图和温升三维图。分析结论为热阻参数是严重影响二维和三维集成电路发展的瓶颈。     

半导体三维集成电路

本文较详细地介绍了制作半导体三维集成电路的三种方法,即回熔再结晶法、叠层法和异质绝缘层法。此外,对三维集成的其它方法还做了扼要的说明。     

面向三维集成电路版图设计的EDA插件研究

三维集成是未来微电子系统的发展方向。但是,现阶段的EDA软件如Cadence等却没有覆盖整个三维集成电路版图设计流程。为了更好的满足工程师在三维集成电路设计中的需要,本文基于SKILL语言,对业界主流版图设计工具Cadence Virtuoso进行二次开发,开发出能辅助三维集成电路设计的EDA插件。该EDA插件主要包括三种功能：自动对齐,自动打孔和三维可视化技术。最终,本文在三维集成电路的背景下设计两个并联的反相器。实验表明,该EDA插件能够满足三维集成电路设计的需求,简化了三维集成电路版图设计的过程,具有很好的易用性。     

三维集成技术的现状和发展趋势

给出了三维技术的定义,并给众多的三维技术一个明确的分类,包括三维封装(3D-P)、三维晶圆级封装(3DWLP)、三维片上系统(3D-SoC)、三维堆叠芯片(3D-SIC)、三维芯片(3D-IC)。分析了比较有应用前景的两种技术,即三维片上系统和三维堆叠芯片和它们的TSV技术蓝图。给出了三维集成电路存在的一些问题,包括技术问题、测试问题、散热问题、互连线问题和CAD工具问题,并指出了未来的研究方向。     

3D集成电路将如何实现？

三维集成电路的第一代商业应用，CMOS图像传感器和叠层存储器，将在完整的基础设施建立之前就开始。在第一部分，我们将回顾三维集成背后强大的推动因素以及支撑该技术的基础设旎的现状，而在第二部分（下期），我们将探索一下三维集成电路技术的商业化。     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

三维微结构制作现状与进展

随着微机电系统(MEMS)的深入研究和快速发展,三维微细加工技术对于微机电的开发和生产具有非常重要的意义.详细介绍了现阶段三维微结构各种制作方法和工艺技术,分析了其原理和特点,比较了各种方法的优劣;讨论了三维微结构开发现状及有待解决的关键技术,综述了利用电子束曝光技术进行三维微结构制作的应用现状并指出了其发展前景.     

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-/spl Omega/ 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 /spl times/ 1024 visible imager with an 8-/spl mu/m pixel pitch, and a 64 /spl times/ 64 Geiger-mode laser radar chip are described.     

SOI技术及其发展和应用

绝缘衬底上的硅(SOI)技术被誉为"21世纪的微电子技术"。它可消除或减轻体硅中的体效应、寄生效应及小尺寸效应等。该文对注氧隔离、键合再减薄、键合和注入相结合及外延层转移等SOI的几种主流制备技术进行了概述,着重介绍了SOI在抗辐照、耐高温等高性能专用电路、光电子、微机械方面以及三维集成电路等领域的主要应用,最后讨论了近几年来SOI技术研究和发展的新动向。     

微电子技术的发展现状与展望

本文分析了微电子技术的发展状况,尤其对集成电路的加工和设计作了较为深入的考察。对本世纪末微电子技术各个领域的发展前景进行了展望。同时,对如何发展我国的微电子技术提出了一些意见和建议。     

Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.     

Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs

Three-dimensional integrated circuits (3-D ICs) offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, and will be, encountered as monolithic process geometries are reduced to below 65 nm. Several methods associated with the fabrication of 3-D ICs are discussed in this paper, and the techniques developed by Tezzaron Semiconductor Corp., are described in detail. Four successful 3-D ICs are described, along with the anticipated benefits of applying 3-D design to future system-on-chip (SoC) devices.     

硅通孔技术的发展与挑战

3D堆叠技术近年来发展迅速,采用硅通孔技术(TSV)是3D堆叠封装的主要趋势.介绍了3D堆叠集成电路、硅通孔互连技术的研究现状、TSV模型;同时阐述了TSV的关键技术与材料,比如工艺流程、通孔制作、通孔填充材料、键合技术等;最后分析了其可靠性以及面临的挑战.TSV技术已经成为微电子领域的热点,也是未来发展的必然趋势,运用它将会使电子产品获得高性能、低成本、低功耗和多功能性.     

Low-leakage germanium-seeded laterally-crystallized single-grain100-nm TFTs for vertical integration applications

We report on 100-nm channel-length thin-film transistors (TFTs) that are fabricated using germanium-seeded lateral crystallization of amorphous silicon. Germanium seeding allows the fabrication of devices with control over grain boundary location. Its effectiveness improves with reduced device geometry, allowing “single-grain” device fabrication. In the first application of this technology to deep submicron devices, we report on 100-nm devices having excellent performance compared to conventional TFTs, which have randomly located grains. Devices have on-off ratio >10⁶ and subthreshold slope of 107 mV/decade, attesting to the suitability of germanium-seeding for the fabrication of high-performance TFTs, suitable for use in vertically integrated three-dimensional (3-D) circuits     

Rapid Fabrication of Soft,Multilayered Electronics for Wearable Biomonitoring

Soft integrated electronics are key components for emerging applications in wearable biomonitoring, soft co‐robotics, and physical human–machine interaction. They are composed of soft and elastically deformable circuits and sensors that are combined with packaged microelectronics for signal processing, power regulation, and communication. While promising, widespread use of soft wearable electronics is currently limited by the lack of robust fabrication techniques to rapidly, efficiently, and precisely assemble soft and rigid components into multilayered systems. Here, an efficient digital fabrication approach is presented to create highly customizable wearable electronics through rapid laser machining and adhesion controlled soft materials assembly. Well aligned, multilayered materials are created from 2D and 3D elements that stretch and bend while seamlessly integrating with rigid components such as microchip integrated circuits, discrete electrical components, and interconnects. These techniques are applied using commercially available materials and components and the fabrication of thin, lightweight, customized sensor skins is demonstrated in under an hour. These fully integrated wireless devices conformably bond to the hand and are successfully used for monitoring hand gesture, pulse rate, and blood oxygenation. These materials and methods enable custom wearable electronics while offering versatility in design and functionality for a variety of applications through material selection and construction.