Analysis of phase accuracy in CMOS quadrature LC oscillators

Using an analytical approach, new estimation of phase error in LC-Tank quadrature oscillators is proposed. The mismatches between passive components of LC tanks are considered as the reasons of the phase error. Closed form equations relating LC mismatches to phase errors are presented. Decreasing quality factor (Q) and increasing coupling factor (k) causes phase error be less sensitive to mismatches in LC tanks. On the other hand phase noise is inversely proportional to quality factor (Q), and directly proportional to coupling factor (k), so there is a tradeoff between phase noise and phase error. To evaluate the analysis, a 5 GHz quadrature LC-Tank oscillator is simulated using TSMC 0.18 μm model technology. The results confirm the simplicity and high accuracy of the proposed analysis.     

CMOS active transformers and their applications in voltage-controlled quadrature oscillators

This paper introduces CMOS active transformers synthesized using MOS transistors only. The proposed active transformers are evolved from their active inductor counterparts and offer a number of attractive characteristics as compared with spiral transformers including a tunable coupling ratio, large and tunable self and mutual inductances, high and tunable quality factors, and a small silicon area consumption. The characteristics of the proposed active transformers including the tunability of the self and mutual inductances, power sensitivity, noise, and quality factor are investigated both analytically and numerically using simulation. The application of the proposed active transformers is exemplified using a 1.6 GHz quadrature VCO implemented in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The total transistor area and power consumption of the VCO are 107 μm² and 10.8 mW, respectively. The phase noise of the VCO is −114.6 dBc/Hz at 1 MHz frequency offset.     

Full oscillation cycle phase noise analysis of differential CMOS LC oscillators

This paper analyzes the phase noise of the widely used differential LC oscillator topology and presents brief equations describing phase noise over the entire oscillation period. The findings show that if a capacitance is present at the source node of the differential pair, two phenomena occur that increase the phase noise: the switch time increases, lengthening the interval spent in a noisy balanced state and increasing the transistor noise excess factor; and at higher frequencies the unbalanced state starts to contribute phase noise. The analysis is based upon the superposition of piecewise linear equations using the EKV transistor model, which includes a concise formulation of the noise excess factor.     

A study of phase noise in CMOS oscillators

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-μm CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB     

Issues on the design and implementation of radio frequency CMOS LC tank voltage-controlled oscillators

This paper is a general tutorial on the design and implementation of integrated submicron CMOS voltage-controlled oscillators based on LC resonator tanks. Although special reference to phase noise reduction is made, the discussion also includes issues such as power consumption, oscillator reliability and adaptivity together with tuning range. Important guidelines on oscillator and LC tank design are discussed, with emphasis on the fact that reduction of noise up-conversion is as important as the reduction of the noise magnitude coming from the various components in the oscillator.     

A study of phase noise in colpitts and LC-tank CMOS oscillators

This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f/sup 2/ phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes of both Colpitts and LC-tank oscillators have been implemented in a 0.35-/spl mu/m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of /spl sim/189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is /spl sim/5 dB lower.     

On the amplitude and phase errors of quadrature LC-tank CMOS oscillators

An analytic approach for the estimation of the phase and amplitude imbalances caused by component mismatches and parasitic magnetic fields in two popular quadrature LC oscillators is presented. Very simple and closed-form equations are derived, proving that, although the two topologies share the same small signal circuit, they display very different sensitivities to the mentioned sources of imbalance. Moreover, it is shown that parasitic inductors coupling, overlooked up to date, plays a key role ultimately limiting the achievable phase accuracy. The theoretical results are verified through extensive simulations and measurements on a 1.7-GHz quadrature oscillator and frequency up-converter implemented in a 0.18-/spl mu/m CMOS process.     

A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy

Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-/spl mu/m CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (IBR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB.     

A time-variant analysis of the 1/f/sup 2/ phase noise in CMOS parallel LC-tank quadrature oscillators

This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis.     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing

This paper reports a low-voltage low-power injection-locked oscillator suitable for short range wireless transmitter applications in a wireless body area network (WBAN). Low-power transmitter with high efficiency is a major design challenge for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows reduced power consumption and high transmitter efficiency. The core block of an injection-locked transmitter is an injection-locked oscillator. In this work a low-voltage low-power injection-locked LC oscillator has been designed and fabricated employing self-cascode structure and body-terminal coupling. The proposed oscillator has been realized using 0.18-μm RF CMOS process. Experimental results indicate that the prototype oscillator can operate with a supply voltage as low as 0.9 V and consumes only 1.4 mW of power. The relatively low-voltage and low-power operation of the design makes it highly suitable for low-power transmitter applications.     

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.     

Minimum achievable phase noise of RC oscillators

To make RC oscillators suitable for RF applications, their typically poor phase-noise characteristics must be improved. We show that, for a given power consumption, this improvement is fundamentally limited by the fluctuation-dissipation theorem of thermodynamics. We also present the analytical formulation of this limit for relaxation (including ring) oscillators using a time-domain phase-noise analysis method which is introduced in this paper. Measurement shows the maximum possible improvement is generally less than 6dB for ring oscillators, while it can be as high as 21dB for other relaxation oscillators. The suboptimal performance of relaxation oscillators is attributed to the continuous current flow in these oscillator topologies. These results provide useful insight for feasibility studies of oscillator design.     

A filtering technique to lower LC oscillator phase noise

Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed     

Intrinsic 1/f device noise reduction and its effect on phase noisein CMOS ring oscillators

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1/f³ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f³ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching     

S波段低相噪振荡器的设计

基于ADS软件仿真,提出了S波段低相噪振荡器的设计方案。该振荡器采用了100MHz低相噪晶体振荡器和倍频链电路的组合,通过三次倍频来实现2GHz的单点频输出,并且在倍频过程中尽量地让相位噪声按照20lgN恶化。实测结果表明,振荡器输出信号的相位噪声在偏移1kHz处可达到-155dBc/Hz,最终输出信功率大于10dBm,谐波抑制大于25dBc。     

Analysis of resonator phase shift for two series LC quadrature VCOs

Based on the investigation of resonator phase shift, an analytical framework to compare the phase noise between two series LC quadrature voltage-controlled oscillators (QVCOs) is presented. The bottom- series QVCO is analytically demonstrated to have lower phase noise than the top-series QVCO. Simulation data show good agreement with the presented analysis.     

A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators

This paper presents both analog and digital automatic-amplitude control techniques for voltage-controlled oscillators (VCOs). These feedback mechanisms help to keep the VCOs at an optimum amplitude over temperature, process, and voltage variations. The VCOs were fabricated in a 50-GHz SiGe BiCMOS process. They use MOS varactors and achieve a 600-MHz tuning range in the 2-GHz band. The phase noise of the VCO with analog control was measured to be -99 dBc/Hz at 100-kHz offset from the carrier. The digital loop allows for a more optimized VCO core that achieves a phase noise of -108.5 dBc/Hz at 100-kHz offset in a low-gain mode. Techniques for suppressing the phase noise in regions of high gain are also presented. The VCOs draw between 4 and 8 mA from a 3.3-V supply.