超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products     

Wafer level system integration: a review

Highlights the major trends and issues affecting monolithic wafer-scale circuits and hybrid wafer-scale circuits, i.e. pretested chips mounted on silicon wafer circuit boards. An extensive set of references is provided to avoid repeating detailed discussions available in the cited literature. Instead, a broad overview of the objectives and motivations of the considerable work on wafer-level system components is provided. It is emphasized that wafer-scale integration provides a foundation on which future systems, perhaps including advanced semiconductor technologies for high-performance components, can achieve evolutionary increases in performance and decreases in system size.<>     

多层圆片级堆叠THz硅微波导结构的制作

基于微电子机械系统(MEMS)工艺,提出一种多层圆片堆叠的THz硅微波导结构及其制作方法。为了验证该结构在制作THz无源器件中的优势,基于6层圆片堆叠的硅微波导结构,设计了一种中心频率365 GHz、带宽80 GHz的功率分配/合成结构,并对其进行了仿真。研究了制作该结构的工艺流程,攻克了工艺过程中的关键技术,包括硅深槽刻蚀技术和多层热压键合技术,并给出了工艺结果。最终实现了多层圆片堆叠功率分配/合成结构的工艺制作和测试。测试结果表明,尽管样品的插入损耗较仿真值增加3 dB左右,考虑到加工误差和夹具损耗等情况,样品主要技术指标与设计值较为一致。     

Characterization of novel mono- and bifacially activesemi-transparent crystalline silicon solar cells

This paper presents the latest cell results for semi-transparent mono- as well as bifacially active POWER (Polycrystalline Wafer Engineering Result) solar cells of different cell sizes on Cz and multicrystalline silicon substrates. Top efficiencies of 10.4% for monofacial and 12.9% for bifacial cells are reported. Attention has been paid to apply a fully industrially compatible production process. It uses dicing saw based mechanical texturization of the front and rear side of the silicon wafer and screen printing metallization. In the POWER solar cell concept, perpendicular grooves on the front and rear side create holes with a variable diameter at their crossing points. This results in a partial optical transparency of the solar cell. In this study, holes of 200 μm diameter lead to a transparency of 16-18% on average for the total cell area. The cell characteristics for the different cell types are compared by means of illuminated and dark current-voltage (I-V), spectral response, and Laser Beam Induced Current (LBIC) measurements. While bifacial POWER cells need a more elaborate production process, they reveal better I-V characteristics and a higher efficiency as compared to monofacial cells. This is mainly explained by a better surface passivation due to an active emitter and a passivating silicon nitride ARC both on the front and rear surface     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。     

扇出型晶圆级封装中圆片翘曲研究

在扇出型晶圆级封装工艺中,由于芯片材料与塑封料之间的热膨胀系数差异,晶圆塑封过程中必然会形成一定的翘曲。如何准确预测晶圆的翘曲并对翘曲进行控制是扇出型晶圆级封装技术面临的挑战之一。在讨论圆片翘曲问题时引入双层圆形板弯曲理论与复合材料等效方法,提出一套扇出型晶圆级封装圆片翘曲理论模型,并通过有限元仿真与试验测试验证了该翘曲理论模型的计算精度。同时给出该理论模型在实际工程中的应用,对扇出型晶圆级封装产品设计与翘曲预测具有指导意义。     

C-MOS/SIS—Using selective SF6etching of {1102} sapphire

A process for selectively etching holes in {1102} sapphire using SF6in H2is described. SiO2, Si3N4, and combinations thereof are studied as possible etchant masks. Refilling the holes with epitaxial silicon produces an SIS (silicon-in-sapphire) wafer wherein the silicon islands are imbedded into the sapphire substrate. The electrical characteristics of C-MOS/SIS transistors are similar to those of conventionally processed SOS devices.     

Wafer-based nanostructure manufacturing for integrated nanooptic devices

The authors have developed a nanomanufacturing platform based on wafer-level nanoreplication with mold and nanopattern transfer by nanolithography. The nanoreplication process, which is based on imprinting a single-layer spin-coated ultraviolet (UV)-curable resist, achieved good nanopatterning fidelity and on-wafer uniformity with high throughput. Some manufacturing issues of the nanoreplication process, such as the impact of wafer and mold surface particles on nanoreplication yield, are also discussed. Nano-optic devices, such as, quarter-wave plates and polarizers, were manufactured with the nanomanufacturing platform. An average wafer-level optical performance yield of 86% was achieved. The developed technology is applied for high-throughput and low-cost manufacturing nanostructure-based optical devices and integrated optical devices.     

Hybridisation of LEDs with silicon microsensors

This paper presents the experiments we performed for hybrid integration of LEDs with silicon optical readout microsensors. LEDs were face down mounted, in a silicon cavity, on the same wafer with the sensor. The edge-emitted light is coupled into SiON waveguides. The LEDs hybridization steps were included in the technological processes of two types of silicon microsensors: chemo-optical and mechano-optical sensors. The proper technological steps succession was established according to the limitation imposed by lithography on wafers with deep groves and the thermal behavior of transducing layers. The main problem we solved was the matching of all the involved processes: integrated optics, micromachining, thin-film technology, CMOS technology.     

Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.     

圆片级真空封装技术在MEMS陀螺中的应用

为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装。制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性。经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8 atm.cm3/s。对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化。     

A Polymer/Carbon‐Nanotube Ink as a Boron‐Dopant/Inorganic‐Passivation Free Carrier Selective Contact for Silicon Solar Cells with over 21% Efficiency

Traditional silicon solar cells extract holes and achieve interface passivation with the use of a boron dopant and dielectric thin films such as silicon oxide or hydrogenated amorphous silicon. Without these two key components, few technologies have realized power conversion efficiencies above 20%. Here, a carbon nanotube ink is spin coated directly onto a silicon wafer to serve simultaneously as a hole extraction layer, but also to passivate interfacial defects. This enables a low‐cost fabrication process that is absent of vacuum equipment and high‐temperatures. Power conversion efficiencies of 21.4% on an device area of 4.8 cm² and 20% on an industrial size (245.71 cm²) wafer are obtained. Additionally, the high quality of this passivated carrier selective contact affords a fill factor of 82%, which is a record for silicon solar cells with dopant‐free contacts. The combination of low‐dimensional materials with an organic passivation is a new strategy to high performance photovoltaics.     

Modular, device-scale, direct-chip-attach packaging formicrosystems

A pressing challenge to the commercial implementation of prototype microsystems is the reduction of package size and cost. To decrease package size, a process was developed for the fabrication of high-aspect-ratio, through-wafer interconnect structures. These interconnects permit device-scale packaging of microsystems and are compatible with modern surface mount technology such as flip chip assembly. To minimize package cost, a modular wafer-level silicon packaging architecture was devised. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications     

深沟槽工艺产品晶片周边硅针缺陷的解决方法

在功率金属氧化物半导体器件生产中,有些为了达到特殊的器件性能,采用深沟槽工艺,其沟槽深度可达几十微米,该类产品在关键的深沟槽刻蚀中,晶片边缘经常会有硅针缺陷产生,该缺陷在后续湿法清洗过程中,会成为颗粒的主要来源,影响晶片良率和污染湿法清洗机台。文章阐述了两种通过优化沟槽光刻工艺来解决此种缺陷的方法,一种为沟槽层光刻采用倒梯形工艺,另一种为沟槽层光刻采用负光阻工艺,两种方法旨在将晶片周边保护起来,在深沟槽刻蚀中下层材质不被损伤,解决深沟槽工艺产品周边硅针缺陷问题。     

一种基于Ag-Sn等温凝固的圆片键合技术

研究了用Ag-Sn作为键合中间层的圆片健合。相对于成熟的Au-Sn键合系统(典型键合温度是280℃),该系统可以提供更低成本、更高键合后分离(De-Bonding)温度的圆片级键合方案。使用直径为100mm硅片,盖板硅片上溅射多层金属Ti/Ni/Sn/Au,利用Lift-off工艺来形成图形。基板硅片上溅射Ti/Ni/Au/Ag。硅片制备好后,将盖板和基板叠放在一起送入键合机进行键合。键合过程在N2气氛中进行,键合过程中不需要使用助焊剂。研究了不同键合参数,如键合压力、温度等对键合结果的影响。剪切强度测试表明样品的剪切强度平均在55.17MPa。TMA测试表明键合后分离温度可以控制在500℃左右。He泄漏测试证明封接的气密性极好。     

硅片CMP抛光工艺技术研究

介绍了硅片机械-化学抛光技术,重点分析了10.16 cm硅片抛光加工过程中抛光液的pH值、抛光压力和抛光垫等因素对硅片抛光去除速率及表面质量的影响.通过试验确定了硅片抛光过程中合适的工艺参数,同时对抛光过程中出现的各种缺陷进行了分析总结,并提出了相应的解决方案.     

再流焊工艺中表面组装片式元件热传输特性模拟

采用有限元数值计算方法，对表面组装件的典型结构进行了对流再流焊的瞬态热模拟，以清晰、直观的等温线图描绘了再流焊各阶段温度的分布，可定量地了解表面组装件热传输特性。本方法可用于ＳＭＴ再流焊工艺（温度曲线）的优化和温度曲线的计算机辅助设计，有助于提高ＳＭＴ的成品率与产品的可靠性。     

抛光工艺对硅片表面Haze值的影响

随着超大规模集成电路的快速发展,硅片表面的Haze值对于现代半导体器件工艺的影响也越来越受到人们的重视.通过实验研究了精抛光工艺参数对硅片表面Haze值的影响规律.结果表明,随着抛光时间的延长,硅的去除量逐渐增大,硅片表面Haze值逐渐降低;同时抛光过程中机械作用与化学作用的协同作用对Haze值也有较大影响.随着抛光液温度的降低与抛光液体积流量的减小,化学作用减弱,硅片表面Haze值逐渐减小.而随着抛光压力的增大,机械作用逐渐起主导作用,硅片表面Haze值逐渐降低.但当Haze值降低到某一数值后,随着硅去除量的增大、抛光液温度的下降、抛光液体积流量的降低、抛光压力的增大,硅片表面的Haze值基本保持不变.     

Extraction of wafer-level defect density distributions to improveyield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDD's per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis