Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment     

Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies

The effect of thermomechanical properties of underfill and compliant interposer materials, such as coefficient of thermal expansion (CTE) and stiffness (Young's modulus) on reliability of flip chip on board (FCOB) and chip scale packages (CSPs) under thermal cycling stresses is investigated in this study. Quasi-three-dimensional viscoplastic stress analysis using finite element modeling (FEM) is combined with an energy partitioning (EP) model for creep-fatigue damage accumulation to predict the fatigue durability for a given thermal cycle. Parametric FEM simulations are performed for five different CTEs and five different stiffnesses of the underfill and compliant interposer materials. The creep work dissipation due to thermal cycling is estimated with quasi 3-D model, while 3-D model is used to estimate the hydrostatic stresses. To minimize the computational effort, the 3-D analysis is conducted only for the extreme values of the two parameters (CTE and stiffness) and the results are interpolated for intermediate values. The results show that the stiffness of the underfill material as well as the CTE play important role in influencing the fatigue life of FCOB assemblies. The fatigue durability increases as underfill stiffness and CTE increase. In the case of compliant interposers, the reverse is true and durability increases as interposer stiffness decreases. Furthermore, the interposer CTE affects the fatigue durability more significantly than underfill CTE, with durability increasing as CTE decreases. The eventual goal is to define the optimum design parameters of the FCOB underfill and CSP interposer, in order to maximize the fatigue endurance of the solder joints under cyclic thermal loading environments.     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

Improved thermal fatigue reliability for flip chip assemblies usingredistribution techniques

The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip     

Humidity and reflow resistance of flip chip on foil assemblies with conductive adhesive joints

The drive toward new first level interconnection technologies is running in parallel with the need to study their reliability as such, as well as in further processes such as second level reflow soldering. Both material properties and process settings have a significant effect on the reliability of adhesive interconnections of flip chips on flexible foil substrates. Integrated circuits (ICs) with pitches of 200 and 300 /spl mu/m bonded on two different foil types were subjected to various moisture preconditioning treatments, and subsequently reflow soldered. Measurements of the daisy chain resistance are used to monitor the yield before and after reflow testing, and to qualify the endurance behavior in the 85/spl deg/C/85% RH stress test. We address here the possible failure mechanisms.     

100 μm Pitch flip chip on foil assemblies with adhesive interconnections

In this work the reliability of flip-chip-on-flexible substrate packages with electrically conductive adhesive as first level interconnections is studied. The pitch of the interconnections ranges from 300 to 100 μm with prospects to smaller pitches. The Physics-of-Failure approach is used to determine the nature of such an interconnection and hence the factors that will influence the performance of these packages. The results indicate that moisture is a more important stress factor than temperature. In particular cyclic exposure to high and low moisture levels may lead to degradation of the electrical interconnection. As failure mechanism, reduction of the compressive force that holds the interconnection together is proposed. Further, the proper combination of materials––based on their in- and out-diffusion rates for water––determines the resistance of the packages to reflow-soldering.     

倒装芯片封装技术及内部应力检测技术探析

当前,倒装芯片封装技术已经成为相关领域的主流方法,但由于芯片、基板、焊球、下填料等材料具有差异化的热膨胀系数,导致封装过程中极易引入热应力,不利于保持芯片的性能及其可靠性。采用有效方法能够对倒装封装过程中所产生的应力进行检测,对于完善封装参数,提高产品可靠性,具有重要的现实意义。     

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation.Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ～25 °C, ～40 °C and ～65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.     

Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages

The work presented in this paper focuses on the behavior of anisotropically conductive film (ACF) joint under the dynamic loading of flip chip on glass (COG) and flip chip on flexible (COF) substrate packages. Impact tests were performed to investigate the key factors that affect the adhesion strength. Scanning electron microscopy (SEM) was used to evaluate the fractography characteristics of the fracture. Impact strength increased with the bonding temperature, but after a certain temperature, it decreased. Good absorption and higher degree of curing at higher bonding temperature accounts for the increase of the adhesion strength, while too high temperature causes overcuring of ACF and degradation at ACF/substrate interface––thus decreases the adhesion strength. Higher extent of air bubbles was found at the ACF/substrate interface of the sample bonded at the higher temperature. These air bubbles reduce the actual contact area and hence reduce the impact strength. Although bonding pressure was not found to influence the impact strength significantly, it is still important for a reliable electrical interconnect. The behaviors of the conductive particles during impact loading were also studied. From the fracture mode study, it was found that impact load caused fracture to propagate in the ACF/substrate interface (for COG packages), and in the ACF matrix (for COF packages). Because of weak interaction of the ACF with the glass, COG showed poor impact adhesion.     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

倒装芯片互连结构中电流聚集研究

由于电流聚集,在倒装芯片封装技术中,电迁移已经成为一个关键的可靠性问题。分析了电迁移力和电迁移中值失效时间,采用二维模型研究了电流密度和焦耳热在倒装芯片互连结构中的分布以及影响电流密度和焦耳热分布的因素。结果表明铝线(Al)和凸点下金属层(UBM)的厚度对电流密度和焦耳热分布有很大的影响。     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the I_ON current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.     

Impact of probing procedure on flip chip reliability

Probe-after-bump is the primary probing procedure for flip chip technology, since it does not directly contact the bump pad, and involves a preferred under bump metallurgy (UBM) step coverage on the bump pads. However, the probe-after-bump procedure suffers from low throughputs and high cost. It also delays the yield feedback to the fab, and makes difficult clarification of the accountability of the low yield bumped wafer between the fab and the bumping house. The probe-before-bump procedure can solve these problems, but the probing tips may over-probe or penetrate the bump pads, leading to poor UBM step coverage, due to inadequate probing conditions or poor probing cards. This work examines the impact of probing procedure on flip chip reliability, using printing and electroplating bumpings on aluminum and copper pads. Bump height, bump shear strength, die shear force, UBM step coverage, and reliability testing are used to determine the influence of probing procedure on flip chip reliability. The experimental results reveal that bump quality and reliability test in the probe-before-bump procedure, under adequate probing conditions, differ slightly from the corresponding items in the probe-after-bump procedure. UBM gives superior step coverage of probe marks in both probe-before-bump and probe-after-bump procedures, implying that UBM achieves greater adhesion and barrier function between the solder bump and the bump pad. Both printing and electroplating bump processes slightly influence all evaluated items. The heights of probe marks on the copper pads are 40–60% lower than those on the aluminum pads, indicating that the copper pad enhances UBM step coverage. This finding reveals that adequate probing conditions of the probe-before-bump procedure are suited to sort flip chip wafers and do not significantly affect bump height, bump shear strength, die shear force, or flip chip reliability.     

倒装芯片凸焊点的UBM

介绍了倒装芯片凸焊点的焊点下金属（UBM）系统,讨论了电镀Au凸焊点用UBM的溅射工艺和相应靶材、溅射气氛的选择,给出了凸焊点UBM质量的考核试验方法和相关指标。     

Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies