Higher-level techniques for hardware description and synthesis

The FLaSH (Functional Languages for Synthesising Hardware) system allows a designer to map a high-level functional language, SAFL, and its more expressive extension, SAFL+, into hardware. The system has two phases: first we perform architectural exploration by applying a series of semantics-preserving transformations to SAFL specifications; then the resulting specification is compiled into hardware in a resource-aware manner – that is, we map separate functions to separate hardware functional units (functions which are called multiple times become shared functional units). This article introduces the SAFL language and shows how program transformations on it can explore area-time trade-offs. We then show how the FLaSH compiler compiles SAFL to synchronous hardware and how SAFL transformations can also express hardware/software co-design. As a case study we demonstrate how SAFL transformations allow us to refine a simple specification of a MIPS-style processor into pipelined and superscalar implementations. The superset language SAFL+ (adding process calculi features but retaining many of the design aims) is then described and given semantics both as hardware and as a programming language. Published online: 17 December 2002     

Generic LR fuzzy cells for fuzzy hardware synthesis

A novel primitive cell structure for high-performance hardware realization of fuzzy computations is proposed in this paper. Such a cell structure is called generic LR fuzzy cell because it is an integral unit that encapsulates an LR fuzzy set and a basic fuzzy operation such as implication or arithmetic operation. Based on the proposed cell structure, we can develop two major kinds of fuzzy cell-LR fuzzy implication cell and LR fuzzy arithmetic cell-for the systematic synthesis of fuzzy application specific integrated circuits (ASICs) or general purposed fuzzy processors. The fuzzy systems synthesized with LR fuzzy cells possess the characteristics of decentralized knowledge manipulations and massively parallel inference. The system expandability and reconfigurability are also warrantable. This paper emphasizes on the design and application of fuzzy implication cell. The LR fuzzy implication cell is implemented with analog current mode technology. By this technology, an implication cell has the characteristics including small circuit area, high performance, low-power dissipation, etc. Moreover, the implication cell manipulates continuous data so that the realization of a pure fuzzy system is possible. In this paper, the key circuit characteristics of fuzzy implication cell are evaluated in details and there are two cases-fuzzy knowledge system and fuzzy mean filter-implemented to confirm the effectiveness and efficiency of fuzzy hardware synthesis by the LR fuzzy cells     

Automatic synthesis of communication controller hardware fromprotocol specifications

Controllers for serial protocols are control-oriented designs that include complex state machines. Manually designing protocol controllers is thus tedious, error prone, and time-consuming. We present a new methodology for the efficient design of communication controller hardware suited for (but not limited to) complex, bit-serial protocols. Our methodology synthesizes controller hardware from a formal high-level specification of the protocol. In this approach, a single run of the synthesis algorithm synthesizes a complete communication architecture from a single protocol specification. The method not only reduces modeling effort but also ensures that both the interacting transaction producer and consumer controllers conform to the initial protocol specification     

Types and associated type families for hardware simulation and synthesis

In this article we overview the design and implementation of the second generation of Kansas Lava. Driven by the needs and experiences of implementing telemetry decoders and other circuits, we have made a number of improvements to both the external API and the internal representations used. We have retained our dual shallow/deep representation of signals in general, but now have a number of externally visible abstractions for combinatorial and sequential circuits, and enabled signals. We introduce these abstractions, as well as our abstractions for reading and writing memory. Internally, we found the need to represent unknown values inside our circuits, so we made aggressive use of associated type families to lift our values to allow unknowns, in a principled and regular way. We discuss this design decision, how it unfortunately complicates the internals of Kansas Lava, and how we mitigate this complexity. Finally, when connecting Kansas Lava to the real world, the standardized idiom of using named input and output ports is provided by Kansas Lava using a new monad, called Fabric. We present the design of this Fabric monad, and illustrate its use in a small but complete example.     

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis

We present SpExSim, a software tool for quickly surveying legacy code bases for kernels that could be accelerated by FPGA-based compute units. We specifically aim for low development effort by considering the use of C-based high-level hardware synthesis, instead of complex manual hardware designs. SpExSim not only exploits the spatially distributed model of computation commonly used on FPGAs, but can also model the effect of two different microarchitectures commonly used in C-to-hardware compilers, including pipelined architectures with modulo scheduling. The estimations have been validated against actual hardware generated by two current HLS tools.

     

On hardware synthesis and implementation of PLC programs in FPGAs

Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units.     

Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis

In high-level synthesis of VLSI circuits,good lower bound prediction can efficiently narrow down the large space of possible designs.Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG),and result in inaccuracy of the lower bound.The loop folding and conditional branch were also not considered,In this paper,a new stepwise refinement algorithm is proposed.which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constratints,Processing techniques to handle multi-cycle,chaining,pipelining,as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm.Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.     

硬件

内存自动降频到333MHz 前几天我又购买了两条二手256MB DDR400内存，再加原来电脑上的两条256MB DDR400内存，内存容量终于达到了1GB。但我在A8N—SLI主板上安装好4条内存之后，开机画面却显示内存频率为333MHz，这是为什么呢？     

硬件

磁盘无法整理碎片：我在对C盘进行磁盘碎片整理时，系统提示：“C：／WINDOWS／prefetch＼WMIPRVSE．EXE-28F301A9．pf”文件损坏，导致扫描不能进行。但是我整理其他分区时部正常，请问这是什么原因呢？     

硬件

硬盘分区问题 Q 最近我为了升级Vista操作系统，特地去购买了一块160GB的大硬盘。安装Vista系统到底需要多大的硬盘空间呢？160GB的硬盘我应该如何分区？     

硬件

正确设置虚拟内存；双核电脑是否需要“双核电源”；在老主板上使用大容量硬盘；让DVD刻录光盘上的数据保存更久；Temp1、Temp2、Temp Sens0含义。     

硬件

内存条插反；刻录时出现错误；数据是否会丢失；系统速度逐渐变慢；3Danalyzer提高显卡性能.[编者按]     

硬件

电脑通电就自动启动；升级显卡之后发现画面亮度降低；如何将CPU和散热器分开；释放笔记本的隐藏分区；Ssmpron 3000＋如何开启CNQ功能；WinXP总是安装错误的网卡驱动；主板PS/2键盘口损坏。     

硬件

波晶显示器无法启动；Win2003里无法使用摄像头；内存的CL值；nForce2主板使用移动硬盘出错；U盾无法正常使用。     

硬件

解决内存的SPD参数不一致；DVI和D-Sub的画质差距是否明显；如何使用双光驱；CPU超频之后不稳定。     

网络

为何有很多MSN联系人添加我为好友；如何在局域网更新NOD32；接力下载无种的BT文件；批量下载网易相册中的相片；让淘宝中的商品按价格自动排序。[编者按]     

硬件

P35主板二次启动问题 Q我使用的是双敏狙击手P35主板,超频之后在开机时会出现二次重启的现象,请问这是什么原因,可以解决吗？