An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

Self-aligned GaAs p-channel enhancement mode MOS heterostructurefield-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga₂O₃ gate oxide, an undoped Al_0.75Ga_0.25As spacer layer, and undoped In_0.2Ga_0.8As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g_m of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

CMOS device isolation using the selective-etch-and-refill-with-EPI (SEREPI) process

A technique has been developed for forming wells in a silicon substrate for CMOS IC's with an oxide layer providing lateral isolation between adjacent devices. The silicon in the wells is etched; oxide is formed on the sidewalls of the wells; and the wells are refilled with selectively deposited epitaxial silicon. Ring oscillators and submicrometer n- and p-channel MOS transistors have been fabricated using this isolation technique, and special latch-up test structures have been investigated.     

Trench-isolated transistors in lateral CVD epitaxial silicon-on-insulator films

Completely dielectrically isolated, p-channel MOS transistors have been obtained by lateral chemical vapor deposition (CVD) epitaxial overgrowth of buried oxide layers and subsequent lateral isolation with refilled trenches. The transistor characteristics are similar to those in bulk control wafers. Isolation between the device island and the substrate is approximately 10¹²Ω.     

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.     

Electrical and structural properties of pulse laser-annealed polycrystalline silicon films

Doped epitaxial films of Si on single-crystal high-resistivity Si substrates have been prepared using ion implantation and Q-switched ruby laser annealing of LPCVD polycrystalline Si layers. Films, doped with B or As in the range 10¹⁷to 5 × 10²⁰cm^-3were studied by the measurement of their resistivities, Hall mobilities, and doping density profiles. The good film quality achieved permitted the fabrication of p-channel MOS transistors which, through measurements of threshold voltage and transconductance, yielded additional data on the surface mobility and the integrity of the Si-SiO2interface. The electrical properties of the films compared favorably with those of similarly doped single-crystal material, and transmission electron microscopy was used to confirm the good structural quality of the epitaxial growth.     

A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application

For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser crystallization process to grow perfect single-crystal Si layers on the amorphous dielectric Si dioxide layers. The SRAM cell size is $ hbox{36} hbox{F}^{2}$ and 0.36 $muhbox{m}^{2}$ with 100-nm complementary MOS technology. The 3-D SRAM cell consists of three differently layered and 3-D stacked-cell thin-film transistors (TFTs), whose channel area is a perfect single-crystal Si. The electrical characteristics of the pass n-channel MOS TFT and the load p-channel MOS TFT are very close to those of the planar bulk transistors because their channel Si layers are perfect single-crystal films. A 500-MHz high-performance and highly cost effective 72-Mb-density 3-D SRAM, which is comparable to the conventional planar 6T SRAM in electrical performance, was successfully fabricated for a stand-alone and embedded memory, with this 3-D stacked 6T SRAM cell technology, the low-temperature TFT formation process, periphery-only Co salicidation, and the W shunt wordline scheme.      

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Performance of CMOS devices in silicon-on-sapphire films after solid-phase epitaxial growth with rapid electron-beam heating

The crystal quality of 0.3-µm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 10¹⁵ions/cm²at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistor mobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation.     

p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Selective low-pressure silicon epitaxy for MOS and bipolar transistor application

The selective low-pressure epitaxy is presented in this paper. In contrast to LOCOS technology, this process starts with structuring a thick field oxide by anisotropic RIE etching. Then monocrystalline silicon is grown selectively in the windows formed. Si-gate MOS transistors have been produced using this technology. In the field of bipolar transistors, reactive ion etching and selective low-pressure epitaxy has been used to optimize the Schottky collector transistor to a nearly one-dimensional structure. These transistors have been built on a submicrometer epitaxial layer.     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

IGBT negative gate capacitance and related instability effects

For high collector voltages, Insulated Gate Bipolar Transistors (IGBTs) exhibit a negative gate capacitance. In this condition, a p-channel inversion layer is formed on the N-base surface. The positive charges in the p-channel induce negative charges in the MOS gate electrode. This results in a negative gate capacitance. As a consequence of this negative capacitance, IGBT operation is inherently unstable, leading to current redistribution between cells or even chips     

Fabrication of Si MOSFET's using neutron-irradiated Silicon as semi-insulating substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The mobility of carrier in the channel is about 100 cm²/V . s for p-channel MOSFET's and 300 cm²/V . s for n-channel devices. This structure has inherent advantages such as crystallographically single crystalline.     

Threshold voltage variations with temperature in MOS transistors

Variations with temperature in the threshold voltage of n- and p-channel MOS transistors are obtained by calculation as well as measurement, with the results comparing quite closely. The amount of voltage change per °C under normal operating conditions is found to be dependent upon the channel doping concentration. The calculations show that for either n- or p-channel devices the voltage change per °C is -4 mV/°C for an impurity concentration of 3 × 10¹⁶/cm³and -2 mV/°C for an impurity concentration of 10¹⁵/cm³. This information is important because if the MOS transistor is subjected to a changing temperature environment, the accompanying threshold voltage change may be intolerable.     

Si-gate CMOS devices on a Si lateral solid-phase epitaxial layer

Si-gate CMOS devices fabricated on a lateral solid-phase epitaxial Si layer grown from vacuum-deposited amorphous Si over SiO₂ patterns are discussed. Electrical characteristics are examined and correlated with microstructural characteristics of the layer by performing transmission electron microscopy on actual transistors. The layer can be divided into three regions. Carrier mobilities obtained from each region are discussed in terms of the crystalline quality. The maximum obtained field-effect mobilities are 570 cm²/V-s and 160 cm²/V-s for n-channel and p-channel transistors, respectively. The SMOS inverter chain with 100 stages and a channel length of 1.5 μm has a delay time of 310 ps per gate. These results indicate that the lateral solid-phase epitaxy has potential for the fabrication of high-speed silicon-on-insulator devices