Electron beam induced current investigations of active electrical defects in silicon due to reactive ion etching and reactive ion beam etching processes

Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results.     

The effect of cathode materials on reactive ion etching of silicon and silicon dioxide in a CF4 plasma

Silicon and silicon dioxide have been Reactive Ion Etched in a CF₄ plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities to the RF cathode were between 0.1 and 1.0 W/cm². The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations for these experimental results will be discussed.     

Reactive ion etching of trenches in 6H-SiC

In this paper, we report the reactive ion etching (RIE) of trenches in 6H-silicon carbide using SF₆/O₂. The plasma parameters: etchant composition, gas flow rate, chamber pressure, and radio frequency power were optimized to obtain a maximum etch rate of 360Å/min. The etch rate of SiC was found to exhibit a direct correlation with the dc self bias except when the O₂ percentage was varied. Trenches were fabricated using the optimized conditions. It was found that the trench surface was extremely rough due to the aluminum micromasking effect. To overcome this effect, a Teflon^TM sheet was used to cover the cathode during the experiment. The trenches fabricated using this modification were found to have smooth etched surfaces and sidewalls. The angle of anisotropy of these trenches was approximately 80° which is suitable for device applications.     

InSb阵列探测芯片的感应耦合等离子反应刻蚀研究

利用感应耦合等离子（ICP）反应刻蚀（RIE）进行了InSb阵列芯片台面刻蚀,并利用轮廓仪、SEM及XRD对台面形貌以及刻蚀损伤进行分析。采用优化的ICP刻蚀参数,实现的刻蚀速率为70~90 nm/min,刻蚀台阶垂直度~80°,刻蚀表面平整光滑、损伤低。与常规的湿法腐蚀相比,明显降低了侧向钻蚀。台面采用此反应刻蚀工艺,制备了具有理想I-V特性的320×256 InSb探测阵列芯片,在-500 mV到零偏压范围内,光敏元（面积23 μm×23 μm）的动态阻抗（Rd）大于100 MΩ。     

Surface contamination and damage from CF4 and SF6 reactive ion etching of silicon oxide on gallium arsenide

Two reactive ion etchants, CF₄ and SF₆, have been compared in terms of plasma characteristics, silicon oxide etch characteristics, extent of RIE damage, and formation of barrier layers on a GaAs surface after oxide etch. It was found that higher etch rates with lower plasma-induced dc bias can be achieved with SF₆ plasma relative to CF₄ plasma and that this correlates with higher atomic fluorine concentration in SF₆ plasma. RIE damage, measured by loss of sheet conductance in a thin highly-doped GaAs layer, could be modelled as a region of deep acceptors at a high concentration in the conductive layer. By relating the sheet conductance change to the modelled damaged layer thickness, it was found that the RIE-damaged thickness from both CF₄ and SF₆ plasmas had the same linear relation to plasma dc bias. Barriers to subsequent GaAs RIE were created during oxide overetch at the GaAs surface. The barriers were identified by XPS as ∼20 A of GaF₃ for CF₄ plasma and ∼30 A of GaF₃ on top of As_xS_y for SF₆ plasma. Ellipsometry was used to routinely determine the presence or absence of the barriers which could be removed in dilute ammonia.     

钛扩散铌酸锂平面波导的反应离子刻蚀

Reactive ion etching（RIE） of LiNbO₃（LN） in SF₆ plasma atmosphere was studied for optimizing the preparation conditions for LN ridge waveguides.The samples to be etched are Ti-diffused LN slab waveguides overlaid with a chromium film mask that has a Mach-Zehnder interferometer（MZI） array pattern.The experimental results indicate that the LN-etching rate(R_LN) and the Cr-etching rate(R_Cr) as well as the rate ratio R_LN/R_Cr increase with either increasing the radio-frequency（RF） power at a given SF₆ flow rate or increasing the SF₆ flow rate at a fixed RF power.The maximum values of R_LN = 43.2 nm/min and R_LN/R_Cr = 3.27 were achieved with 300 W RF power and 40 sccm SF₆ flow.When the SF₆ flow rate exceeds 40 sccm,an increase in the flow rate causes the etching rates and the rate ratio to decrease.The scanning electron microscope images of the LN ridge prepared after～20 min etching show that the ridge height is 680 nm and the sidewall slope angle is about 60°.     

反应离子刻蚀InSb芯片引入的损伤研究

应用CH₄/H₂/Ar作为刻蚀气源对InSb微台面阵列进行了反应离子刻蚀,并对刻蚀后引入的损伤进行了分析。实验证实利用干法刻蚀与湿法腐蚀相结合的方法能有效地减少刻蚀引入的缺陷和损伤,获得较好的电学特性,达到低损伤刻蚀InSb材料的目的。     

Carbon reactions in reactive ion etched silicon

Reactive ion etching (RIE) of silicon creates interstitial defects in the near surface region which diffuse into the bulk material and are trapped at substitutional carbon sites. Photoluminescence (PL), current-voltage (I–V), and Rutherford backscattering (RBS) measurements show that silicon etched in a CF₄ + 8%O₂ or SF₆ + 8%O₂ plasma consists of two distinct regions, adisplacement damage region extending 1000Å from the surface and apoint defect reaction region which can extend to depths > 1 μm. The size of the point defect reaction region is determined by diffusion limited trapping of the interstitial silicon generated during the RIE resulting in the formation ofC _i - O_i orC _s -C_i defect pairs. The long range diffusion rate of the interstitial defects is enhanced by the plasma during the RIE processing, and by a recombination enhanced reaction path.     

Characterization of selective reactive ion etching effects on delta-doped GaAs/AlGaAs MODFET layers

The effects of selective reactive ion etching (SRIE) using SiCl₄/SiF₄ plasma on delta-doped GaAs/Al_0.3Ga_0.7As modulation-doped field-effect transistor (MODFET) structures and devices have been investigated. The results are compared with those of corresponding conventionally doped MODFETs. Hall measurements were conducted at 300 and 77 K to characterize the change in the transport properties of the two-dimensional electron gas due to low energy ion bombardment during the SRIE process. Delta-doped structures showed a smaller change in sheet carrier density and mobility compared to conventionally doped structures. Direct current and high frequency measurements were performed on the SRIE gate-recessed MODFETs. No significant change in threshold voltage was observed for the delta-doped MODFETs in contrast to an increase of about 300 mV for the conventionally doped MODFETs processed at a plasma self-bias voltage of −90 V and a 1200% overetch time. Maximum dc extrinsic transconductance and unity current gain cutoff frequency did not change with SRIE processing for either of the structures. This paper was presented at the Electronic Materials Conference at MIT, Cambridge, 1992.     

Fabrication of AD/DA microfluidic converter using deep reactive ion etching of silicon and low temperature wafer bonding

The purpose of this work is to describe an original process that has been designed for the fabrication of a microfluidic converter. The fabrication is based on deep reactive ion etching of silicon and low temperature full wafer adhesive bonding. The technology development includes an improvement of the bonding process in order to produce an adaptive strength of SU-8 bond which not only ensures absence of debonding failures during the silicon deep etching procedure and the subsequent dicing procedure, but also avoids the potential SU-8 overflow leakage into channels due to the bonding step. Besides, the originality of the work is not only in the process but also in the design of the device. Common actuation method for microfluidic system is either based on closed-channel continuous-flow microfluidic (CMF) or droplet-based microfluidic (DMF). Both of them have advantages and disadvantages, and their integration on a single system is in dire need. In this paper, we briefly discuss the concept of microfluidic converter, integrating CMF with DMF, which can: (i) continuously preload reagents, (ii) independently manipulate several droplets, (iii) recombine and export samples into closed-channel continuous flow, making it ideal for interfacing to liquid-handling instruments and micro-analytical instruments.     

Reactive ion etching of gallium nitride films

Reactive ion etching (RIE) was performed on gallium nitride (GaN) films grown by electron cyclotron resonance (ECR) plasma assisted molecular beam epitaxy (MBE). Etching was carried out using trifluoromethane (CHF₃) and chloropentafluoroethane (C₂ClF₅) plasmas with Ar gas. A conventional rf plasma discharge RIE system without ECR or Ar ion gun was used. The effects of chamber pressure, plasma power, and gas flow rate on the etch rates were investigated. The etch rate increased linearly with the ratio of plasma power to chamber pressure. The etching rate varied between 60 and 500Å/min, with plasma power of 100 to 500W, chamber pressure of 60 to 300 mTorr, and gas flow rate of 20 to 50 seem. Single crystalline GaN films on sapphire showed a slightly lower etch rate than domain-structured GaN films on GaAs. The surface morphology quality after etching was examined by atomic force microscopy and scanning electron microscopy.     

Vertical silicon membrane arrays patterned with tri-level e-beam resist

A high resolution, tri-level e-beam resist process has been developed which has produced, by liftoff, planar metal features as fine as 25 nm wide by 5 Μm long on thick Si substrates. The metal features have been used as masks for transfer of the pattern into the substrate itself, producing arrays of Si membranes, 50 nm wide, 0.3 pm high and extending 5 Μm in length. We compare the resolution of the tri-level system with that obtained for a previously reported bi-level system of similar composition.     

Contamination of silicon and oxidized silicon wafers during plasma etching

Neutron activation analysis has been used to study the type and level of contamination of silicon and oxidized silicon wafers exposed to various plasmas used in silicon device processing. Silicon wafers exposed to plasmas in a reactor previously used to remove SiN passivation layers from Au metallized wafers were found to be heavily contaminated with Au (up to ∼10¹⁴ atoms/cm²). Au contamination of oxidized silicon wafers similarly treated was two to three orders of magnitude smaller regardless of whether SiO₂ etched faster or slower than Si in the plasmas used. Wet chemical cleaning of contaminated Si subsequent to plasma exposure was relatively ineffective in removing residual Au. This is interpreted as indicating indiffusion of Au during plasma exposure of Si. Exposure to a polymer forming plasma reduced the level of Au contamination of Si by nearly two orders of magnitude due to effective “sealing” of reactor surfaces by polymer film. Further, the level of contamination of Si was observed to decrease by over two orders of magnitude with usage time of the reactor during a 300-day time period when no Au containing materials were introduced into the reactor.     

Fabrication of sharp silicon tips employing anisotropic wet etching and reactive ion etching

We developed a process to obtain sharper silicon tips by employing anisotropic etching in a KOH solution followed by SF₆ plasma etch. The tips were further sharpened using the established thermal oxidation technique to decrease the cone angle and, therefore, obtain smaller curvature radii. We have analyzed the impact of such changes in geometry on a figure of merit associated with the field emission characteristics. An increase in the figure of merit by a factor of three was found in relation to the tips before sharpening.     

黑硅无掩模反应离子刻蚀法制备及光学性能研究

采用无掩模反应离子刻蚀法制备了黑硅.利用扫描电子显微镜及紫外-可见-近红外分光光度计研究了黑硅的微结构和光学特性.结果表明,黑硅微结构高度为2.0～3.5 μm,径向尺寸90～400 nm,间距200～610 nm.在400～1 000 nm光谱范围内黑硅吸收率为94％,是单晶硅的1.5倍;在1 200～1 700 nm光谱范围吸收率为55％～60％,是B掺杂单晶硅的20倍.制备的黑硅的光学带隙为0.600 6 eV,吸收光谱明显向红外方向偏移.     

Nanometer fabrication in mercury cadmium telluride by electron cyclotron resonance microwave plasma reactive ion etching

It has been recently reported (J.R. Meyer, F.J. Bartoli, C.A. Hoffman, and L.R. Ram-Mohan,Phys. Rev. Lett. 64, 1963 [1990]) that novel electronic and optical effects are anticipated in nanometer scale features of narrow band gap semiconductors such as mercury cadmium telluride (MCT). These efforts could lead to the creation of non-linear optical switches, high efficiency infrared lasers, and unique nanoelectronic devices. This work reports on the first realization of MCT nanostructures through the application of e-beam lithography and reactive ion etching with an electron cyclotron resonance (ECR) microwave plasma source. It is shown that the low energy ions produced by an ECR system can etch MCT with good selectivity over an e-beam resist mask and with high resolution. Using these fabrication methods, 40–70 nm features with aspect ratios of 3–5∶1 and sidewall angles greater than 88° have been demonstrated. Qualitative investigations of some of the etch mechanisms of this technique are made, and results suggest a desorption limited process. ^*Code 6675,^†Code 5613,^‡Code 6864     

Stencil-assisted reactive ion etching for micro and nano patterning

Stencil-assisted oxygen reactive ion etching is a low-cost and parallel process for the replication of micrometric and nanometric patterns in any organic material. This lithography process allows the patterning of organic material non sensitive to electronic or optical radiations, sensitive to solvents, or already patterned which cannot be patterned by conventional lithography methods. We demonstrate the versatility of stencil-assisted reactive ion etching though 3 examples. First to define 500 nm holes in PMMA. Secondly, the fabrication step has been integrated in a lift-off process of metal or molecular self-assembled monolayers. We finally apply stencil-assisted reactive ion etching to pattern an assembly of 100 nm latex nanoparticles.     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。     

Ionic liquid ion sources for silicon reactive machining

In this article the authors report on ionic liquid ion sources (ILISs) for silicon reactive machining and direct microfabrication of silicon structures. The authors have developed a specific source geometry using the ionic liquid EMI-BF4 to obtain stable emission currents up to the 10 μA regime. ILIS EMI-BF4 engraving properties were then investigated in low and high current regime showing very different etching characteristics. The results and the chemical analysis of the patterned substrates suggest that reactive ion species can be generated from ILIS. This possibility is of major interest to allow decisive advances in the field of focused ion beam applications.     

Uniformity in HgCdTe diode arrays fabricated by reactive ion etching

Two-dimensional, midwavelength infrared (MWIR) HgCdTe detector arrays have been fabricated using reactive ion etching (RIE). Detector-to-detector uniformity has been studied in the devices fabricated with CdTe- and ZnS-passivation layers. Mapping of the doping profile, passivant/HgCdTe interface electrical properties, and diode impedance-area product (R₀A_j) in a two-dimensional array of diodes has been carried out. Temperature and perimeter/area dependence of the dark current are studied to identify the bulk and surface current components. Maximum R₀A_j=2×10⁷ Θcm² was achieved in CdTe-passivated, 200×200 μm² diode arrays. It demonstrates that CdTe-passivated, RIE-processed HgCdTe is a feasible technology.