Analysis and reduction of signal readout circuitry temporal noisein CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 μm CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data     

A 128×128-pixel standard-CMOS image sensor with electronicshutter

A 128×128-pixel image sensor with a 20 s-10^-4 s electronic shutter has been integrated in a 1.2-μm digital CMOS technology. The pixel cell consists of four PMOS transistors and a photodiode with antiblooming suppression. Each pixel measures 24 μm by 24 μm and has a fill factor of 25%. Current is used to transfer pixel signals to the column readout amplifiers in order to minimize voltage swings on the highly capacitive column lines. Correlated double sampling is used to reduce intracolumn fixed pattern noise. The saturation voltage is 470 mV. The peak output signal to noise ratio is 45 dB, and the optical dynamic range is 56 dB. The frame transfer rate is 1.7 ms per frame     

Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors

The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture.     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

High-performance CMOS buffered gate modulation input (BGMI) readoutcircuits for IR FPA

A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×10⁷ electrons, the transimpedance of 2.5×10⁹ Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm². These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively     

A low-voltage CMOS complementary active pixel sensor (CAPS)fabricated using a 0.25 μm CMOS technology

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a V_DD below 1 V with a reasonable output swing     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization     

红外微弱信号的放大与调理电路设计

从热电堆红外探测器的检测电路设计入手,讨论了微弱信号的放大和调理方法,分析了热电堆探测器输出信号的时频域特性和噪声,给出了各环节的实现电路并进行了仿真,分析了以前置放大器为主的模拟信号链的噪声,并提出了噪声匹配的新方法,最终实现了微弱信号的测量。测试结果表明,本电路在噪声抑制和失调补偿方面达到了理想的效果,最小可检测到3.5μV的微弱直流信号变化,在红外光谱探测以及微弱直流信号检测中可以有较广泛的应用。     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Improved a-Si:H TFT pixel electrode circuits for active-matrixorganic light emitting displays

Two improved four thin-film-transistors (TFTs) pixel electrode circuits based on hydrogenated amorphous silicon (a-Si:H) technology have been designed. Both circuits can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The circuit simulation results indicate that an excellent linearity between the output current and input current can be established. An output current level higher than ~5 μA can be achieved with these circuits. This current level can provide a pixel electrode brightness higher than 1000 cd/m² with the organic light-emitting device (OLED) having an external quantum efficiency of 1%. These pixel electrode circuits can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs)     

Low-power current-mode 0.9-V voltage regulator

A design for a low-power integrated 0.9-V voltage regulator for load currents up to 140 μA is presented. The circuit contains no external components and it stabilizes the voltage of a single battery cell of 1.1-1.6 V with a PSRR >40 dB over a frequency range of up to 30 kHz. The regulating circuit operates a current level and accomplishes automatic load-current limiting. Its r.m.s output noise is <4 μV over a frequency range of 10 Hz-8 kHz. The quiescent supply current is ≈40 μA     

An image-rejecting mixer and vector filter with 55-dB imagerejection over process, temperature, and transistor mismatch

This paper describes an image-rejecting mixer and vector filter for use in radio systems with channel bandwidths in the range of 1 MHz. The circuit replaces the SAW filter and second downconverter commonly used in this style of radio. Because the output of the circuit is at an IF of 5 MHz, traditional demodulation methods including limiting and FM discrimination can still be used. The circuit is based on a quadrature mixer that guarantees good performance despite device mismatches and process variation. The circuit consumes 29 mA at 3.3 V,and achieves better than 55-dB image rejection despite device mismatches and process variation and is implemented in a single-poly triple metal 0.5 μm CMOS process with linear capacitor implants. The circuit is designed for input signals from 125 to 250 MHz. Input referred voltage noise is 900 μVrms. The in-band IP3 is 18 dBm. By changing an external reference frequency, the passband width of the filter can be varied from 3 to 0.5 MHz     

320×256大电荷容量的长波红外读出电路结构设计

长波红外探测器存在暗电流大、背景高的特点,需要设计大电荷容量的读出电路。采用分时共享积分电容的电路结构,在面阵焦平面的有限单元面积中设计了一种高读出效率、大电荷容量的320256长波红外焦平面读出电路。电路输入级采用电容反馈跨阻放大器（CTIA）结构,具有注入效率高、噪声低、线性度好的特点。基于CSMC 0.35 m标准CMOS工艺模型进行了模拟仿真以及版图设计完成后的后端仿真,电路输出电压范围大于2 V,非线性小于1%,帧频为100 f/s,采用分时共享积分电容电路结构后,像元有效电荷容量达到57.5 Me-/像元。     

320×256中/长波双色IRFPAs读出电路设计

中波与长波探测器的光电流及动态输出阻抗存在数量级的差别。为满足积分时间及读出信号信噪比的要求,采用像元间多电容共享的方案,设计了一种高集成度的320256双色红外焦平面读出电路。该电路选用直接注入(DI)结构作为中波输入级,而长波输入级则选用了缓冲注入(BDI)结构。其缓冲放大器采用单边结构,具有高增益、低功耗、低噪声的特点,降低了输入阻抗,提高了注入效率。基于HHNEC 0.35 m 2P4M标准CMOS工艺,完成了芯片的设计与制造。经测试,引入电容共享方案后其有效电荷容量达到70 Me-/像元,电路各项功能正常,在光照条件下,芯片呈现出高的灵敏性。在2.5 MHz读出速率下,中波及长波输出电压范围均大于2 V,非线性小于1%。在100 f/s帧频下,整体功耗小于170 mW。     

一种驱动MOS管工作在饱和区的硅基OLED微显示像素电路

硅基OLED微显示中为了在极小的像素面积内实现微小的OLED工作电流,其像素驱动电路的驱动MOS管一般工作在亚阈值区,存在OLED电流对驱动MOS管的阈值电压和栅源电压失配敏感、外围电路复杂等问题,如果驱动MOS管工作在饱和区则可避免这些问题,但为了获得微小的驱动电流,必须采用尺寸大的倒比MOS管,这又与极小的像素面积冲突。本文提出了一种采用脉宽调制(PWM)技术、驱动MOS管工作在饱和区的OLED微显示像素驱动电路,PWM信号减少了一帧内OLED的实际工作时间,OLED的脉冲电流变大,使驱动MOS倒比管的尺寸减小;由于PWM信号占空比小,同时实现了OLED微小的平均像素驱动电流和亮度。结果表明PWM信号占空比为3%时,实现的OLED驱动电流和像素亮度范围分别为27pA~2.635nA、2.19~225.1cd/m~2,同时采用双像素版图共用技术,在15μm×15μm的像素面积内实现了像素驱动电路的版图设计。     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color