Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Design and performance of multistage GaAs dynamic logic

GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation     

CMOS数字电路低功耗的层次化设计

随着芯片上可以集成越来越多的管子,电路规模在不断扩大,工作频率在不断提高,这直接导致芯片功耗的迅速增长,无论是从电路可靠性来看,还是从能量受限角度来讲,低功耗都已成为CMOS数字电路设计的重要内容。由于不同设计抽象层次对电路功耗的影响不同,对各有侧重的低功耗设计方法和技术进行了讨论,涉及到工艺,版图,电路,逻辑,结构,算法和系统等不同层次。在实际设计中,根据具体应用环境,综合不同层次全面考虑功耗问题,可以明显降低电路功耗。     

低功耗双边沿触发器的逻辑设计

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能,能够正常地应用于时序电路的设计,并且由于时钟工作频率减半而导致系统功耗的明显降低．     

The Future Impact of GaAs Digital IC's

A review of digital GaAs IC technology and an assessment of its future impact on gigabit signal processing is presented. High-speed signal processing and computers will require MSI-complexity interface circuits capable of 1-10 GHz clock frequencies and LSI-complexity digital circuits operating in the 0.2-5 GHz range at tens of microwatts per gate. A wide range of applications exists for frequency counters, multiplexers, A/D converters, FFT's, microprocessors, and memories that operate at speeds significantly higher than on presently available circuits. Issues related to high-speed IC design such as power dissipation, packing density, capacitance effects, design rules, and intra- and interchip propagation delays are discussed.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A high speed GaAs error-detection circuit for fiber-optictransmission systems

A high-speed GaAs IC for detection of line code vibrations is described. This 144-gate error-detection circuit for monitoring a high-bit-rate fiber-optic link has been designed and fabricated using a high-yield titanium tungsten nitride self-aligned gate MESFET process. This process routinely provides a wafer-averaged gate delay (fan-in=fan-out=2) of less than 70 ps with a power dissipation of 0.5 mW/gate. The error-detection circuits were tested on-wafer using high-frequency probe cards at a clock rate of 1.4 GHz, with a yield of 64%. Packaged circuits worked at a clock frequency of over 2.5 GHz and consumed 200-mW power at a fixed power supply voltage of 1.5 V. The circuits operate over a wide variation in power supply voltage and temperature. When operated at a package temperature of 125°C, the circuits show less than a 12% degradation in their maximum clock frequency. The circuit was inserted into a 565-Mb/s system currently using a silicon ECL part, and full functionality was verified with no necessary modifications     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

Low-power multi-threshold MCML: Analysis, design, and variability

The increasing demand on low-power applications is adding pressure on circuit designers to come out with new circuit styles that can decrease power dissipation while making use of the performance improvement of the new CMOS technologies. Multi-threshold MOS current mode logic (MTMCML) appears to be a solution to this problem by making use of the high-performance of MOS current mode circuits while minimizing power dissipation with the help of multi-threshold CMOS technologies. In this work, analytical formulations, based on the BSIM3v3 model, are proposed for MTMCML performance measures with an error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.     

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.     

Self-aligned AlInAs-GaInAs heterojunction bipolar transistors andcircuits

AlInAs-GaInAs heterojunction bipolar transistors (HBTs) and static flip-flop frequency dividers have been fabricated. An f_t and an f_max of 49 and 62 GHz, respectively, have been achieved in a device with a 2×5-μm² emitter. Current-mode logic (CML) was used to implement static divide-by-two and divide-by-four circuits. The divide-by-two circuit operated at 15 GHz with 82-mW power dissipation for the single flip-flop. The divide-by-four circuit operated at 14.5 GHz with a total chip power dissipation of 444 mW     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

Transimpedance receiver design optimization for smart pixel arrays

Optical transimpedance receivers implemented in CMOS VLSI technologies are modeled and optimized for freespace optoelectronic interconnections. Sensitivity, bandwidth, power dissipation, and circuit area are analyzed for receivers using three different submicron CMOS processes. A comparison with the circuit noise limited optical power indicates that, for digital computing applications, the receiver sensitivity is limited by the gain-bandwidth product of the receiver amplifiers and the necessary noise margin of logic circuits     

Quantum flux parametron (QFP) shift registers clocked by aninductive power distribution network and errorless operation of the QFP

The authors present 4- and 12-b shift registers capable of operating from DC up to 8.56 and 4.24 GHz, respectively. These circuits' total on-chip power dissipation is estimated to be roughly 10 nW. A novel clock current distribution network permits such high clock frequency and such low on-chip power dissipation. The clock is applied as a standing wave and is distributed by inductive division. With this clock current distribution scheme, no power is dissipated along the clock lines. In spite of the circuits' low output amplitude (tens of microvolts) and of the large crosstalk with the clock frequency, the output waveforms are captured in time domain at microwave frequencies. Also, for the 12-b device, 10¹⁵ error free operations per quantum flux parametron (QFP) are demonstrated. Finally, the 12-b shift register is the largest QFP circuit reported to date; it is composed of 48 QFPs and one DC SQUID     

USB数据传输中CRC校验码的并行算法实现

文章介绍了用于USB总线数据传输的CRC校验的原理和算法，并且采用并行电路实现USB2．0中的CRC产生和CRC校验，与传统的串行电路实现相比，并行电路实现方法虽然在芯片面积上大于串行电路实现，但由于降低了时钟频率，电路更容易综合实现，并且大大降低了功耗，有利于低功耗电路设计。     

Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology

Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse fields, such as low-power design, optical information processing, and quantum computation. In this paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh-Wooley approach, which are much better than the two available counterparts in all the terms. The multiplier is an essential building block for the construction of computational units of quantum computers. Besides, we need signed multiplier circuits for numerous operations. However, only two reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All the proposed circuits are in the nanometric scales and can be used in the design of very complex systems.     

可逆逻辑表达式的识别和图示方法

可逆逻辑电路是仅包含可逆运算的新型电路,还可根除源于信息损失的能耗和发热,是研究与实现超低功耗集成电路、量子计算机及信息安全等的关键基础。文中针对可逆逻辑电路研究的需要,研究了通过识别可逆逻辑表达式提取可逆逻辑电路结构信息,并加以图形化显示的有效方法和可行算法,以便更形象、直观地表达可逆逻辑电路综合、优化的结果,进而为分析、理解和优化可逆逻辑电路提供方便。     

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits     

Debugging reversible circuits

A strong driving force for research of post-CMOS technologies is the fact that silicon-based transistors cannot be arbitrarily scaled down. Furthermore, power dissipation is a major barrier in the development of smaller and more efficient computer chips. In contrast, reversible logic with its applications e.g. in low-power design or quantum computation provides a promising alternative to traditional technologies. While there have been investigations in the domain of reversible logic synthesis, testing, and verification; debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior.In this paper, we propose the first approach for automatic debugging of reversible Toffoli circuits. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to traditional (irreversible) debugging. In addition, we introduce an improved approach that strengthens error candidate identification. This overcomes the limitations from traditional debugging, i.e. that error candidates are only an approximation of the real source of the error. Furthermore, observations are presented that can be applied to automatically fix an erroneous circuit just by replacing a single gate by a cascade. Due to reversibility this cascade can be efficiently computed. Experimental results show the quality and efficiency of our debugging approaches.     

High-speed demonstration of single-flux-quantum cross-bar switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.