Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

A very high precision 500-nA CMOS floating-gate analog voltage reference

A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.     

Low-leakage current, low-area voltage regulator for system-on-a-chip processors

A low-leakage current, low-area voltage regulator for system-on-a-chip processors is proposed. The system is demonstrated in a 0.13 /spl mu/m CMOS technology with a supply voltage varied between 0.8 and 1.5 V. Using this system, the leakage current and power are reduced by as much as 44/spl times/ and 33/spl times/, respectively, compared to conventional topologies.     

Built-in current sensor for /spl Delta/I/sub DDQ/ testing

This paper presents the implementation of a built-in current sensor for /spl Delta/I/sub DDQ/ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) enabling versatile testing strategy through the implementation of two advanced /spl Delta/I/sub DDQ/ testing algorithms. The monitor has been manufactured in a 0.18-/spl mu/m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 /spl mu/A for a background current less than 100 /spl mu/A or 1% of background currents over 100 /spl mu/A to a total of 1-mA full scale. The sensor operates at a maximum clock speed of 250 MHz. The quiescent current is indirectly determined by counting a number of clock pulses which occur during the time the voltage at the disconnected node drops below a reference voltage value. Basically, at the end of the count period, the counted value is inversely proportional to the quiescent current of the device under test. Then, a /spl Delta/I/sub DDQ/ unit processes the counted number and the outcome is compared with a reference number to determine whether a defect exists in the device under test. Accuracy is improved by adjusting the value of the reference number and the frequency of the clock signal depending upon the particular process corner of the circuit under test. The monitor has been verified in a test chip consisting of one "DSP-like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.     

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.     

CMOS low dropout linear regulator with single Miller capacitor

A 2-5V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 /spl mu/m CMOS process and the active chip area is 485/spl times/586 /spl mu/m. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers

An accurate CMOS current source for current-mode low-voltage differential transmitter drivers has been designed and fabricated. It is composed of binary weighted current mirrors with built-in self-calibration circuits. The proposed self-measurement and calibration circuits can calibrate upon the collective effects of different error contributors due to process, power supply, and temperature variations. The design has been fabricated in standard 0.35-/spl mu/m CMOS technology. Measurement results show that the differential output voltage can be self-calibrated to /spl plusmn/1% accuracy with 16% reference current variation, 60% power supply variation, or 13% load resistance variation, respectively.     

A 44-/spl mu/W 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range

A microwatt frequency divider for the 2.5-GHz ISM band is proposed. This divider directly modulates the output in a ring oscillator by means of a switch and realizes low power consumption with low supply voltage and a wide locking range. It is fabricated using a five-layer-metal and 0.2-/spl mu/m-gate length CMOS process. The core size is 10.8/spl times/10.5 /spl mu/m/sup 2/, which is much smaller than that of a typical inductor-enhanced frequency divider. This divider operates with a supply voltage in the range from 1.8 to 0.7V, and attains minimum power consumption of 44 /spl mu/W, in which case the supply voltage is 0.7 V, the maximum operating frequency is 4.3 GHz, and the locking range is 2.3 GHz. A derivation of the frequency locking range of the divider is provided in the Appendix.     

Dual tone and modem frequency generator with on-chip filters and voltage reference

A single-chip CMOS circuit is described that contains a dual-tone multifrequency and modem frequency generator. For optimum performance and economy, switched-capacitor techniques are used for the on-chip bandgap reference voltage, digital-to-analog converters, and filter. CEPT recommendations on output level stability and distortion are met without recourse to external filtering and without a stabilized supply or external reference voltage. A self-aligned contact CMOS process with 4-/spl mu/m design rules and with 500-/spl Aring/-thick gate oxide is used to manufacture the circuit.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.