量子纠错电路的模块化设计与优化

在无测量状态下,对三量子位纠错电路进行设计和优化,提出模块化概念设计和优化量子纠错电路。随着量子位的增加,三量子位纠错电路作为模块可用于五量子位纠错电路中,五量子位纠错电路作为模块可用于七量子位纠错电路中,以此类推。少量子位纠错电路作为多量子位纠错电路的部分模块使用,可使得多量子位纠错电路设计简化,冗余位减少,使之量子代价较低。     

ADS—B系统应答的一种纠错算法设计与实现

ADS—B是基于ModeS数据链的一种技术,可以为传统雷达无法覆盖的区域提供监视服务。本文介绍了基于模式S的ADS—B系统基带数字信号处理流程,阐述了循环冗余编码（CRC）的工作原理。基于模式S的ADS-B系统,提出了一种基于循环冗余编码（CRC）的纠错算法;然后给出了纠错算法的FPGA实现方案,整个设计划分为多个功能...     

基于置信度的S模式信号随机多位纠错技术

针对现有纠错技术只能对少量随机错误或突发错误进行纠错的不足,提出了一种基于置信度的随机多位纠错方法。该方法在准确进行置信度判断的基础上,通过缩短循环冗余校验（CRC）处理时间或增加并行运算能力以增加纠错位数。同时给出了可运用于工程实际的保守技术和强力技术的联合纠错处理流程。通过解码纠错实验,统计结果表明该置信度判定法则的准确性为98.24%,通过图形处理器（GPU）强力纠错可实现高达83.37%的解码率,通过现场可编程门阵列（FPGA）强力纠错可实现73.66%的解码率,较现有强力纠错技术的纠错能力有较大提高,可增强对航空器监视的连续性。     

用VHDL设计CRC发生器和校验器

用VHDL设计了一个在数字传输中常用的校验、纠错模块———循环冗余校验CRC模块 ,完成数据传输中的差错控制。通过时序仿真波形可看出 ,当输入 12位信息位时 ,通过CRC发生器和校验器 ,可得到准确的输出     

用VHDL设计CRC发生器和校验器

用VHDL设计了一个在数字传输中常用的校验、纠错模块--循环冗余校验CRC模块,完成数据传输中的差错控制.通过时序仿真波形可看出,当输入12位信息位时,通过CRC发生器和校验器,可得到准确的输出.     

用VHDL设计CRC发生器和校验器

用VHDL设计了一个在数字传输中常用的校验、纠错模块--循环冗余校验CRC模块,完成数据传输中的差错控制.通过时序仿真波形可看出,当输入12位信息位时,通过CRC发生器和校验器,可得到准确的输出.     

基于VHDL的混合差错控制方案

混合纠错是数字通信中用于差错控制的主要方式之一.本文分析了汉明码（Hamming code）与循环冗余校验（CRC）的特点,提出了将CRC码和汉明码结合在一起实现混合纠错的方案,并根据CRC及汉明码的编译码特点及纠错原理,用硬件描述语言VHDL对其功能进行了描述,给出了程序的主要源代码及仿真结果.结果显示,这种混合纠错方式不仅可以纠正1位错码,还能检测出多位错码.     

一种利用CRC改善路由器传输性能的方法

分析循环冗余校验码CRC的数学原理和检错纠错能力，提出了一种在不改变现有路由器传输系统结构的情况下，利用CRC的单比特纠错能力提高传输性能的新方案，并给出了方案的实现方法和性能的仿真结果。     

SDH信号中的ATM信元实时检测算法

HEC段信息同整个ATM信头有关,利用8位循环冗余编码方式(CRC校验码)产生,用于单比特纠错和多比特查错.针对国内外广泛使用的SDH网络,利用HEC段功能进行SDH帧数据中ATM信元的识别,为SDH网络中ATM信元协议分析和重组的奠定基础.由于信元识别是基于信元本身的差错控制字段,所以能有效地提高识别性能,降低最大信元丢失率.     

一种改进的循环冗余校验纠错技术

通常传统上使用蛮力纠检错的方法来纠正接收数据中存在的随机错误.现以ADS-B的S模式数据链为例,分析了蛮力纠错方法在实践应用中存在的局限和不足,并根据这些局限和不足给出了一种纠错预处理的方法,将这种方法结合蛮力纠检错方法使用,在不改变编码的情况下大大增强了循环冗余校验码的纠错能力.     

Design of parallel fault-secure encoders for systematic cyclic block transmission codes

In this paper, we consider the problem of designing parallel fault-secure encoders for various systematic cyclic linear codes used in data transmission. It is assumed that the data to be encoded before transmission are stored in a fault-tolerant RAM memory system protected against errors using a cyclic linear error detecting and/or correcting code. The main idea relies on taking advantage of the RAM check bits to control the correct operation of the cyclic code encoder as well. A slightly modified encoder allows not only for encoding the transmission data stream but also, independently and in parallel, to generate the reference check bits which allow for concurrent error detection in the encoder itself. The error detection capacity proves to be effective and grants good levels of protection as shown by error injection campaigns on encoders for various standard linear cyclic error detecting and error correcting codes. Moreover, the complexity evaluation of the FPGA implementations of the encoders shows that their fault-secure versions compare favorably against the unprotected ones, both with respect to hardware complexity and the maximal frequency of operation.     

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories

This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of the code correction ability and efficiency. Furthermore, we will show that a minimal increase in the redundancy with respect to the standard case allows a further considerable reduction of the impact on memory access time and area overhed due to the error correction circuitry.     

On forward error correction with adaptive decoding (Corresp.)

A method is proposed that utilizes punctured Reed-Solomon (RS) block codes for adaptive coding. Part of the redundancy of the RS codewords is used in a convolutional coding framework. This enables some codewords to use more redundancy for correcting errors, while other adjacent codewords use less redundancy.     

The design and performance of a neural network for predicting turbodecoding error with application to hybrid ARQ protocols

It is shown that a neural network can be trained to observe the cross entropy of the outputs of component decoders in a turbo error control system and to accurately predict the presence of errors in the decoded data. The neural network can be used as a trigger for retransmission requests at either the beginning or the conclusion of the decoding process, providing improved reliability and throughput performance at a lower average decoding complexity than turbo decoding with cyclic redundancy check error detection     

The burst error correcting capabilities of a simple array code

We propose a simple decoder for a widely used array code, known as the EVENODD code, which is originally designed to correct phased burst errors, to make it useful for correcting nonphased errors. The proposed scheme is capable of correcting almost all bursts up to a certain length. We show that the failure rate is sufficiently small and approaches zero as the block length increases. The redundancy of the code is twice the maximal burst length, which is a lower bound for the redundancy of a true burst-error-correcting code. Both the encoder and the decoder have very low complexity, both in terms of number of operations and in terms of computer code size     

A diversity combining DS/CDMA system with convolutional encodingand Viterbi decoding

Averaged diversity combining is applied to an asynchronous DS/CDMA system using convolutional encoding and Viterbi decoding. A cyclic redundancy check (CRC) code is included in the scheme to trigger retransmission requests. Multiple received packets are combined on a bit by bit basis to form a single, more reliable packet. The error correcting decoder operates on the combined packet, as opposed to the most recently received individual packet (e.g., as in a type-I hybrid ARQ protocol), substantially increasing the probability of acceptance with each additional transmission. We show that the proposed technique allows a significant increase in the CDMA system capacity, throughput, and reliability     

字节式单向错误纠错码

介绍了一种有效的字节式单向错误纠错码及其编码和译码算法。从对校验位数下限值的讨论可以看出,这里介绍的码优于字节式对称错误纠错码,并且近似最优。本文还介绍了字节式非对称错误纠错码。     

Arithmetic coding-based continuous error detection for efficientARQ-based image transmission

Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new “continuous” error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection, first introduced by Bell, Witten, and Cleary (1990), is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error     

A Data Transmission Method Using a Cyclic Redundancy Check and Inaudible Frequencies

This paper describes a data transmission method using a cyclic redundancy check and inaudible frequencies. The proposed method uses inaudible high frequencies from 18 kHz to 22 kHz generated via the inner speaker of smart devices. Using the proposed method, the performance is evaluated by conducting data transmission tests between a smart book and smart phone. The test results confirm that the proposed method can send 32 bits of data in an average of 235 ms, the transmission success rate reaches 99.47%, and the error detection rate of the cyclic redundancy check is 0.53%.