Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

High-mobility poly-Si TFTs fabricated on flexible stainless-steelsubstrates

High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO₂ films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO₂ films are sputter-deposited in oxygen atmosphere from the SiO₂ target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm²/V·s and drain current on-off ratio of as high as 1×10⁶. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

Optimizing polysilicon thin-film transistor performance withchemical-mechanical polishing and hydrogenation

Chemical-mechanical polishing and hydrogen passivation were jointly used to improve the electrical characteristics of polycrystalline-Si thin-film transistors (poly-Si TFT's). It was found that each treatment affects the devices differently; polishing is more effective in smoothing the poly-Si/SiO₂ interface while hydrogenation is more effective in passivating the grain boundaries. Their effects are additive. Hence, optimal device performance was achieved by combining both treatments     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of SiO2

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO₂ was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO₂ C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO₂ C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm²/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

High-mobility poly-Si thin-film transistors fabricated by a novelexcimer laser crystallization method

High-mobility poly-Si thin-film transistors (TFTs) were fabricated by a novel excimer laser crystallization method based on dual-beam irradiation. The new method can reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO₂/Si/glass substrate structure by means of laser irradiation not only from the front side but also from the back side. The grain size of poly-Si film was enlarged up to 2 μm. The field-effect mobilities of the TFT exceeded 380 cm²/V-s for electrons and 100 cm²/V-s for holes     

An analytical method of evaluating variation of the thresholdvoltage shift caused by the negative-bias temperature stress in poly-SiTFTs

The variation of the threshold voltage shift (V_th shift) caused by negative-bias temperature stress (-BT stress) in poly-crystalline silicon thin-film transistors (poly-Si TFTs) was investigated. Based on the chemical reaction caused by -BT stress at the poly-Si/SiO₂ interface and the poly-Si grain boundary, an analytical method of evaluating the variation of both the V_th shift and the initial V_th was proposed. It was shown from this analysis that the enlargement of the poly-Si grain, using Si₂ H₆ gas could be a solution for efficient reduction of the easily hydrogenated dangling bonds which resulted in the V_th shift and suppression of the V_th shift and its variation. Moreover, it was suggested that there are two kinds of the dangling bonds; one is hydrogenated by hydrogenation and can be dehydrogenated by -BT stress; the other is not hydrogenated and the variation of its density is much smaller than the former     

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $hbox{Pr}_{2}hbox{O}_{3}$ Gate Dielectric

In this paper, we have developed high-k Pr₂O₃ poly-Si thin-film transistors (TFTs) using different N₂O plasma power treatments. High-k Pr₂O₃ poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high I_ON/I_OFF current ratio. This result is attributed to the smooth Pr₂O₃/poly-Si interface and low interface trap density. Pr₂O₃ poly-Si TFT with a 200-W N₂O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr₂O₃ gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs.     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Hydrogenation of polysilicon thin-film transistor in a planarinductive H2/Ar discharge

A planar inductive discharge is used to hydrogenate polysilicon thin-film transistors (poly-Si TFTs). Experimental results indicate that inductive discharges operate at higher plasma densities, thereby capable of shortening the hydrogenation time, in addition, to promote the ionization of hydrogen, Ar gas is also introduced to H₂ plasma during hydrogenation. Furthermore, we discuss the mechanism of Ar enhanced hydrogenation and the characteristics of H₂/Ar mixed plasma. Moreover, the post-hydrogenation anneal is utilized to further enhance passivation efficiency and improve the reliability of poly-Si TFTs     

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g_m) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5×10⁹ and very low leakage current of the order of 10¹⁴ A can be achieved by these high-performance TFTs     

Improving the Electrical Properties of NILC Poly-Si Films Using a Gettering Substrate

Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (alpha-Si) has been employed to fabricate poly-crystalline silicon (poly-Si) thin-film transistors. However, current crystallization technology often leads to Ni and NiSi₂ precipitates being trapped, thus degrading the performance of the device. We proposed using alpha-Si-coated wafers as Ni-gettering substrates. After bonding the gettering substrate with the NILC poly-Si film, both the Ni-metal impurity within the NILC poly-Si film and the leakage current were greatly reduced, thus increasing the ON/OFF current ratio.