MOS Characteristics of C-Face 4H-SiC

Metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated on the carbon face of 4H-SiC were characterized following different postoxidation annealing methods used to passivate the oxide–semiconductor (O–S) interface. Of the various processes studied, sequential postoxidation annealing in NO followed by atomic hydrogen gave the lowest interface trap density (D _it). Direct oxidation/passivation in NO yielded somewhat better I–V characteristics, though all passivation ambients produced approximately the same breakdown field strength. n-Channel MOSFETs showed high channel mobility at low field, which is likely caused by the presence of mobile ions at the O–S interface. Comparisons with the silicon face are presented for interface trap density, oxide breakdown field, and channel mobility. These comparisons suggest that the carbon face does not offer significant performance advantages.     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

Interfacial properties and reliability of SiO2 grown on 6H-SiC in dry O2 plus trichloroethylene

A new process of growing SiO₂ on n- and p-type 6H-SiC wafers in dry O₂ + trichloroethylene (TCE) was investigated. The interface quality and reliability of 6H-SiC metal-oxide-semiconductor (MOS) capacitors with gate dielectrics prepared by the process were examined. As compared to conventional dry O₂ oxidation, the O₂ + TCE oxidation resulted in lower interface-state, border-trap and oxide-charge densities, and enhanced reliability. This could be attributed to the passivation effect of Cl₂ or HCl on structural defects at/near the SiC/SiO₂ interface, and the gettering effect of Cl₂ or HCl on ion contamination. In addition, increased oxidation rate was observed in the O₂ + TCE ambient, and can be used to reduce the normally-high thermal budget for oxide growth. All these are very attractive for fabricating SiC MOS field-effect transistors (MOSFETs) with high inversion-channel mobility and high hot-carrier reliability.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

Effects of wet oxidation/anneal on interface properties ofthermally oxidized SiO2/SiC MOS system and MOSFET's

Effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC. Deep interface states and fixed oxide charges were mainly discussed. The wet atmosphere was effective to reduce a negative flatband shift caused by deep donor-type interface states in p-type SiC MOS capacitors. Negative fixed charges, however, appeared near the interface during wet reoxidation anneal. In n-type SIC MOS capacitors, the flatband shift indicated a positive value when using wet atmosphere. The relation between interface properties and characteristics of n-channel planar 6H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was also investigated. There was little relation between the interface properties of p-type MOS capacitors and the channel mobility of MOSFETs. The threshold voltage of MOSFETs processed by wet reoxidation anneal was higher than that of without reoxidation anneal. A clear relation between the threshold voltage and the channel mobility was observed in MOSFETs fabricated on the same substrate     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

Investigation of 4H-SiC MOS capacitors annealed in diluted N2O at different temperatures

Thermally grown oxide on 4H-SiC has been post-annealed in diluted N₂O (10% N₂O in N₂) at different temperatures from 900 to 1100 °C. The quality of the nitrided oxide and the SiO₂/4H-SiC interface was investigated by AC conductance and high frequency C-V measurements based on Al/SiO₂/4H-SiC metal-insulator-semiconductor (MOS) structure. It is found that N₂O annealing at 1000 °C produces the lowest interface state density, though the difference is not so significant when compared to the other samples annealed at 900 and 1100 °C. These results can be explained by the high temperature dynamic decomposition process of N₂O. By fitting the AC conductance data, it is found that higher temperature nitridation increases the capture cross-section of the interface traps.     

High channel mobility in inversion layers of 4H-SiC MOSFETs byutilizing (112¯0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112¯0) face: 17 times higher (95.9 cm²/Vs) than that on the conventional (0001) Si-face (5.59 cm²/Vs). A low threshold voltage of MOSFETs on the (112¯0) face indicates that the (112¯0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (μ_(11¯00)/μ₍₀₀₀₁₎=0.85) reflects the small anisotropy in bulk electron mobility     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Strong dependence of the inversion mobility of 4H and 6H SiC(0001)MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (ρ(H₂O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also ρ(H₂O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm²/Vs for 4H and 95 cm²/Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a ρ(H₂O) of 50%     

Lateral n-channel inversion mode 4H-SiC MOSFETs

Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm²/V·s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric     

氧化后退火技术对SiO2/4H-SiC界面态密度的影响

采用等离子体增强化学气相沉积(PECVD)低温处理和高温快速退火的技术,研究了退火条件对SiO2/4H-SiC界面态密度的影响.在n型4H-SiC外延片上高温干氧氧化50 nm厚的SiO2层并经N2原位退火,随后在PECVD炉中对样品进行350℃退火气氛为PH3,N2O,H2和N2的后退火处理,之后进行高温快速退火,最后制备Al电极4H-SiC MOS电容.I-V和C-V测试结果表明,各样品的氧化层击穿场强均大于9 MV/cm,PH3处理可以降低界面有效负电荷和近界面氧化层陷阱电荷,但PH3处理样品的界面态密度比N2O处理的结果要高.经N2O氛围PECVD后退火样品在距离导带0.2和0.4 eV处的界面态密度分别约为1.7× 1012和4×1011eV-1·cm-2,有望用于SiC MOSFET器件的栅氧处理.     

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO₂/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

Improved oxidation procedures for reduced SiO2/SiC defects

A significant reduction in the effective oxide charge and interface state densities in oxides grown on p-type 6H-SiC has been obtained by lowering the oxidation temperature of SiC to 1050°C. Further improvements are obtained by following the oxidation with an even lower temperature re-oxidation anneal. This anneal dramatically improves the electrical properties of the Si/SiC interface, and substantially lowers the interface state density. The net oxide charge density on p-type 6H-SiC is also lowered significantly, but remains quite high, at 1.0 × 10¹² cm^-2. The interface state densities of 1.0 × 10¹¹ cnr⁻²/eV are approaching acceptable MOS device levels. The breakdown fields of the oxides are also substantially improved by both the lower oxidation temperature and re-oxidation anneal. Using a low temperature oxidation followed by a re-oxidation anneal for MOSFETs results in a room temperature mobility of 72 cm²/V-s, the highest channel mobility reported for SiC MOSFETs to date.     

Significantly improved performance of MOSFETs on silicon carbideusing the 15R-SiC polytype

Recent studies regarding MOSFETs on SiC reveal that 4H-SiC devices suffer from a low inversion layer mobility, while in 6H-SiC, despite a higher channel mobility the bulk mobility parallel to the c-axis is too low, making this polytype unattractive for power devices. This work presents experimental mobility data of MOSFETs fabricated on different polytypes as well as capacitance-voltage (C-V) measurements of corresponding n-type MOS structures which give evidence that the low inversion channel mobility in 4H-SiC is caused by a high density of SiC-SiO₂ interface states close to the conduction band. These defects are believed to be inherent to all SiC polytypes and energetically pinned at around 2.9 eV above the valence band edge. Thus, for polytypes with band gaps smaller than 4H-SiC like 6H-SiC and 15R-SiC, the majority of these states will become resonant with the conduction band at room temperature or above, thus remarkably suppressing their negative effect on the channel mobility. In order to realize high performance power MOSFETs the results reveal that 15R-SiC is the best candidate among all currently accessible SiC polytypes     

Effect of process variations and ambient temperature on electron mobility at the SiO/sub 2//4H-SiC interface

We report the effect of processing variables on the inversion layer electron mobility of (0001)-oriented 4H-SiC n-channel MOSFETs. The process variables investigated include: i) implant anneal temperature and ambient; ii) oxidation procedure; iii) postoxidation annealing in nitric oxide (NO); iv) type of gate material, and v) high-temperature ohmic contact anneal. Electron mobility is significantly increased by a postoxidation anneal in NO, but other process variations investigated have only minor effects on the channel mobility. We also report the temperature dependence of electron mobility for NO and non-NO annealed n-channel MOSFETs.     

Study of Electron Mobility in 4H-SiC Buried-Channel MOSFETs

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

4H-SiC隐埋沟道MOSFET迁移率的研究

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.