Specific Contact Resistance Measurement of Screen-Printed Ag Metal Contacts Formed on Heavily Doped Emitter Region in Multicrystalline Silicon Solar Cells

Multicrystalline silicon (mc-Si) wafers are widely used to develop low-cost high-efficiency screen-printed solar cells. In this study, the electrical properties of screen-printed Ag metal contacts formed on heavily doped emitter region in mc-Si solar cells have been investigated. Sintering of the screen-printed metal contacts was performed by a co-firing step at 725°C in air ambient followed by low-temperature annealing at 450°C for 15 min. Measurement of the specific contact resistance (ρ _c) of the Ag contacts was performed by the three-point probe method, showing a best value of ρ _c = 1.02 × 10^?4 Ω cm² obtained for the Ag contacts. This value is considered as a good figure of merit for screen-printed Ag electrodes formed on a doped mc-Si surface. The plot of ρ _c versus the inverse of the square root of the surface doping level (N _s ^?½ ) follows a linear relationship for impurity doping levels N _s ≥ 10¹⁹ atoms/cm³. The power losses due to current traveling through various resistive components of finished solar cells were calculated by using standard expressions. Cross-sectional scanning electron microscopy (SEM) views of the Ag metal and doped mc-Si region show that the Ag metal is firmly coalesced with the doped mc-Si surface upon sintering at an optimum firing temperature of 725°C.     

High-resolution direct-writing of metallic electrodes on flexible substrates for high performance organic field effect transistors

We report on organic field-effect transistors (OFETs) with sub-micrometer channels fabricated on plastic substrates with fully direct-written electrical contacts. In order to pattern source and drain electrodes with high resolution and reliability, we adopted a combination of two digital, direct writing techniques: ink-jet printing and femtosecond laser ablation. First silver lines are deposited by inkjet printing and sintered at low temperature and then sub-micrometer channels are produced by highly selective femtosecond laser ablation, strongly improving the lateral patterning resolution achievable with inkjet printing only. These direct-written electrodes are adopted in top gate OFETs, based on high-mobility holes and electrons transporting semiconductors, with field-effect mobilities up to 0.2 cm²/V s. Arrays of tens of devices have been fabricated with high process yield and good uniformity, demonstrating the robustness of the proposed direct-writing approach for the patterning of downscaled electrodes for high performance OFETs, compatibly with cost-effective manufacturing of large-area circuits.     

Fabrication of a <Emphasis Type="Italic">p</Emphasis>–<Emphasis Type="Italic">n</Emphasis> Heterojunction Using Topological Insulator Bi<Subscript>2</Subscript>Te<Subscript>3</Subscript>–Si and Its Annealing Response

A junction device has been fabricated by growing p-type Bi₂Te₃ topological insulator (TI) film on an n-type silicon (Si) substrate using a thermal evaporation technique. Annealing using different temperatures and durations was employed to improve the quality of the film, as confirmed by microstructural study using x-ray diffraction (XRD) analysis and atomic force microscopy (AFM). The p–n diode characteristics of the junction devices were studied, and the effect of annealing investigated. An improved diode characteristic with good rectification ratio (RR) was observed for devices annealed for longer duration. Reduction in the leakage or reverse saturation current (\( I_{\rm{R}} \)) was observed with increase in the annealing temperature. The forward-bias current (\( I_{\rm{F}} \)) dropped in devices annealed above 400°C. The best results were observed for the sample device annealed at 450°C for 3 h, showing figure of merit (FOM) of 0.621 with RR ≈ 504 and \( I_{\rm{R}} \) = 0.25 μA. In terms of ideality factor, the sample device annealed at 550°C for 2 h was found to be the best with \( n \) = 6.5, RR ≈ 52.4, \( I_{\rm{R}} \) = 0.61 μA, and FOM = 0.358. The majority-carrier density \( \left( {N_{\rm{A}} } \right) \) in the p-Bi₂Te₃ film of the heterojunction was found to be on the order of 10⁹/cm³ to 10¹¹/cm³, quite close to its intrinsic carrier concentration. These results are significant for fundamental understanding of device applications of TI materials as well as future applications in solar cells.     

Low‐Temperature‐Processed Printed Metal Oxide Transistors Based on Pure Aqueous Inks

Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InO_x ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InO_x ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R _c < 160 Ω cm) and competitive transistor performance (µ _lin up to 19 cm² V^?1 s^?1, Subthreshold Slope (SS) ≤150 mV dec^?1) with only low‐temperature processing (T ≤ 250 °C).     

Acid etching for accurate determination of dislocation density in GaN

Hot phosphoric-acid etching and atomic force microscopy (AFM) were used to etch and characterize various GaN materials, including freestanding GaN grown by hydride vapor-phase epitaxy (HVPE), metal-organic chemical-vapor deposition (MOCVD) GaN films on sapphire and silicon carbide, and homoepitaxial GaN films on polished freestanding-GaN wafers. It was found that etching at optimal conditions can accurately reveal the dislocations in GaN; however, the optimal etch conditions were different for samples grown by different techniques. The as-grown HVPE samples were most easily etched, while the MOCVD homoepitaxial films were most difficult to etch. Etch-pit density (EPD) ranging from 4×10⁶ cm⁻² to 5×10⁹ cm⁻² was measured in close agreement with the respective dislocation density determined from transmission electron microscopy (TEM).     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Fabrication of High-Temperature-Stable Thermoelectric Generator Modules Based on Nanocrystalline Silicon

High-temperature-stable thermoelectric generator modules (TGMs) based on nanocrystalline silicon have been fabricated, characterized by the Harman technique, and measured in a generator test facility at the German Aerospace Center. Starting with highly doped p- and n-type silicon nanoparticles from a scalable gas-phase process, nanocrystalline bulk silicon was obtained using a current-activated sintering technique. Electrochemical plating methods were employed to metalize the nanocrystalline silicon. The specific electrical contact resistance ρ _c of the semiconductor–metal interface was characterized by a transfer length method. Values as low as ρ _c < 1 × 10^?6 Ω cm² were measured. The device figure of merit of a TGM with 64 legs was approximately ZT = 0.13 at 600°C as measured by the Harman technique. Using a generator test facility, the maximum electrical power output of a TGM with 100 legs was measured to be roughly 1 W at hot-side temperature of 600°C and cold-side temperature of 300°C.     

High Mobility and Stability of Thin-Film Transistors Using Silicon-Doped Amorphous Indium Tin Oxide Semiconductors

We report the fabrication of high-performance thin-film transistors (TFTs) with an amorphous silicon indium tin oxide (a-SITO) channel, which was deposited by cosputtering a silicon dioxide and an indium tin oxide target. The effect of the silicon doping on the device performance and stability of the a-SITO TFTs was investigated. The field-effect mobility and stability under positive bias stress of the a-SITO TFTs with optimized Si content (0.22 at.% Si) dramatically improved to 28.7 cm²/Vs and 1.5 V shift of threshold voltage, respectively, compared with the values (0.72 cm²/Vs and 8.9 V shift) for a-SITO TFTs with 4.22 at.% Si. The role of silicon in a-SITO TFTs is discussed based on various physical and chemical analyses, including x-ray absorption spectroscopy, x-ray photoelectron spectroscopy, and spectroscopic ellipsometry measurements.     

Low-temperature materials and thin-film transistors for electronics on flexible substrates

The deposition processes and electronic properties of thin-film semiconductors and insulators based on silicon in relation to the fabrication of electronic devices on flexible plastic substrates are considered. The films of amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN_x), and also thin-film transistors are fabricated at comparatively low temperatures (120°C, 75°C) using existing commercial plasma-chemical equipment. The parameters of thin-film transistors based on a-Si:H and fabricated at the aforementioned relatively low temperatures are compatible with those of high-temperature analogues.     

Strain Reduction in Selectively Grown CdTe by MBE on Nanopatterned Silicon on Insulator (SOI) Substrates

Silicon-based substrates for the epitaxy of HgCdTe are an attractive low-cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch, which creates strain at the heterointerface that results in a high density of dislocations. Previously we have reported on theoretical modeling of strain partitioning between CdTe and Si on nanopatterned silicon on insulator (SOI) substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a two-dimensional array of silicon pillars with ～250 nm diameter and 1 μm pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS). Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two-step growth process involving desorption of the nucleation layer followed by regrowth of CdTe at a rate of 0.2 Å s^?1. Strain measurements by Raman spectroscopy show a comparable Raman shift (2.7 ± 2 cm^?1 from the bulk value of 170 cm^?1) in CdTe grown on nanopatterned SOI and planar silicon (Raman shift of 4.4 ± 2 cm^?1), indicating similar strain on the nanopatterned substrates.     

Development of 3.7 % Efficient Cu2ZnSnSe4 Solar Cells by Selenizing Cu-Zn-Sn Films Deposited by DC Sputtering on TiN-Protected Mo/Glass Substrates

Cu₂ZnSnSe₄ (CZTSe) films for solar cell devices were fabricated by sputtering of a Cu-Zn-Sn target followed by post-selenization at 500–600 °C for 1 h in the presence of single or double compensation discs to supply Se vapor. The optimized selenization conditions avoided the Se deficiency and enhanced the grain growth of CZTSe films. The 600 °C-selenized CZTSe films adjacent with double discs obtained the large grains of 2–5 μm and had a [Cu]/([Zn]+[Sn]) ratio of 0.94 and a [Zn]/[Sn] ratio of 1.34. In order to fabricate the device on Mo-coated glass substrates, a TiN reaction barrier layer was coated before the Cu-Zn-Sn sputtering coating. The TiN-CZTSe device had 3.7 % efficiency (η), as compared to 0.58 % for the TiN-free one. The efficient device had the CZTSe layer with hole concentration (n _p) of 3.4 × 10¹⁷ cm^?3, Hall mobility (μ) of 54 cm² V^?1 s^?1, and electrical conductivity (σ) of 2.9 Ω^?1 cm^?1.     

Analysis of channel noise and threshold voltage in sos-MOS transistors in the temperature range of 77–300 K

A characterization is carried out for MOS transistors on sapphire on the basis of an analysis of the threshold voltage V_T and the channel noise current using the doping of the silicon (2 × 10¹⁵ cm^?3 to 6 × 10¹⁶ cm^?3) and the temperature (77–300 K) as parameters.The experimental values of V_T, as a function of the bulk potential V_BS, show that it is possible to deplete the silicon film fully for doping magnitudes less than 10¹⁶ cm^?3. The modelling of V_T vs. V_BS, using a relation derived for bulk Silicon devices, points to finite volume effects of the silicon.The analysis of the noise shows, at 300 K, an excess noise which follows a 1/f law for the Silicon film not fully depleted and a 1/f² law in the depleted case. On the other hand, at 77 K, this noise always shows a 1/f behaviour. The study of the noise as a function of temperature suggests that the traps of the Silicon-Sapphire interface become more active around room temperature than around 77 K. The thermal level is reached at about 1 MHz at room temperature for all devices, whereas at 77 K it is only observed for the higher doping devices.     

Properties of ZnO Thin Films Codoped with Lithium and Phosphorus

The properties of ZnO thin films codoped with lithium and phosphorus have been characterized. The films were deposited from high-purity ZnO and Li₃PO₄ solid targets onto c-plane sapphire substrates by radiofrequency (RF) magnetron sputtering. A substrate temperature of 900°C was determined as optimum for depositing undoped ZnO films with background electron concentration of 9.9 × 10¹⁵ cm^?3 as the buffer layer on the sapphire substrate. Postdeposition annealing was carried out using rapid thermal processing in O₂ at temperatures ranging from 500°C to 1000°C for 3 min. Analyses performed using low-temperature photoluminescence spectroscopy measurements revealed luminescence peaks at 3.356 eV, 3.307 eV, 3.248 eV, and 3.203 eV at 12 K for the codoped samples. X-ray diffraction 2θ-scans showed a single peak at about 34.4° with full-width at half-maximum of about 0.09°. Hall-effect measurements revealed initial p-type conductivities, but these were unstable and toggled between p-type and n-type over time with Hall concentrations that varied between 2.05 × 10¹³ cm^?3 and 2.89 × 10¹⁵ cm^?3. The fluctuation in the carrier type could be due to lateral inhomogeneity in the hole concentration caused by stacking faults in the films. An additional cause could be the small Hall voltages in the measurements, which could be significantly impacted by even small spikes in signal noise inherent in the measurements.     

Non-functionalized soluble diketopyrrolopyrrole: Simplest p-channel core for organic field-effect transistors

We report the synthesis, characterization and behavior in field-effect transistors of non-functionalized soluble diketopyrrolopyrrole (DPP) core with only a solubilizing alkyl chain (i.e. –C₁₆H₃₃ or –C₁₈H₃₇) as the simplest p-channel semiconductor. The characteristics were evaluated by UV–vis and fluorescence spectroscopy, X-ray diffraction, cyclic voltammetry (CV), thermal analysis, atomic force microscopy (AFM) and density functional theory (DFT) calculation. For top-contact field-effect transistors, two types of active layers were prepared either by a solution process (as a 1D-microwire) or thermal vacuum deposition (as a thin-film) on a cross-linked poly(4-vinylphenol) gate dielectric. All the devices showed typical p-channel behavior with dominant hole transports. The device made with 1D-microwiress of DPP-R18 showed field-effect mobility in the saturation region of 1.42 × 10^?2 cm²/V s with I_ON/I_OFF of 1.82 × 10³. These findings suggest that the non-functionalized soluble DPP core itself without any further functionalization could also be used as a p-channel semiconductor for low-cost organic electronic devices.     

Interface Microstructure and Performance of Sb Contacts in Bismuth Telluride-Based Thermoelectric Elements

A thermoelectric joint composed of p-type Bi_0.5Sb_1.5Te₃ (BiSbTe) material and an antimony (Sb) interlayer was fabricated by spark plasma sintering. The reliability of the thermoelectric joints was investigated using electron probe microanalysis for samples with different accelerated isothermal aging time. After aging for 30 days at 300°C in vacuum, the thickness of the diffusion layer at the BiSbTe/Sb interface was about 30 μm, and Sb₂Te₃ was identified to be the major interfacial compound by element analysis. The contact resistivity was 3 × 10^?6 ohm cm² before aging and increased to 8.5 × 10^?6 ohm cm² after aging for 30 days at 300°C, an increase associated with the thickness of the interfacial compound. This contact resistivity is very small compared with that of samples with solder alloys as the interlayer. In addition, we have also investigated the interface behavior of Sb layers integrated with n-type Bi₂Se_0.3Te_2.7 (BiSeTe) material, and obtained similar results as for the p-type semiconductor. The present study suggests that Sb may be useful as a new interlayer material for bismuth telluride-based power generation devices.     

Enhanced Thermoelectric Properties of Antimony Telluride Thin Films with Preferred Orientation Prepared by Sputtering a Fan-Shaped Binary Composite Target

p-Type antimony telluride (Sb₂Te₃) thermoelectric thin films were deposited on BK7 glass substrates by ion beam sputter deposition using a fan-shaped binary composite target. The deposition temperature was varied from 100°C to 300°C in increments of 50°C. The influence of the deposition temperature on the microstructure, surface morphology, and thermoelectric properties of the thin films was systematically investigated. x-Ray diffraction results show that various alloy composition phases of the Sb₂Te₃ materials are grown when the deposition temperature is lower than 200°C. Preferred c-axis orientation of the Sb₂Te₃ thin film became obvious when the deposition temperature was above 200°C, and thin film with single-phase Sb₂Te₃ was obtained when the deposition temperature was 250°C. Scanning electron microscopy reveals that the average grain size of the films increases with increasing deposition temperature and that the thin film deposited at 250°C shows rhombohedral shape corresponding to the original Sb₂Te₃ structure. The room-temperature Seebeck coefficient and electrical conductivity range from 101 μV K^?1 to 161 μV K^?1 and 0.81 × 10³ S cm^?1 to 3.91 × 10³ S cm^?1, respectively, as the deposition temperature is increased from 100°C to 300°C. An optimal power factor of 6.12 × 10^?3 W m^?1 K^?2 is obtained for deposition temperature of 250°C. The thermoelectric properties of Sb₂Te₃ thin films have been found to be strongly enhanced when prepared using the fan-shaped binary composite target method with an appropriate substrate temperature.     

Structural and Carrier Dynamics of GaN and AlGaN-Based Double Heterostructures in the UV Region

Aluminum gallium nitride-based double heterostructures with two different active layer widths have been grown on GaN templates by metalorganic chemical vapor deposition. Crystalline quality has been investigated using high-resolution x-ray diffraction analysis, and screw, edge, as well as total dislocation densities in the GaN epilayer have been calculated. The dislocation density of GaN has been found to be on the order of 10⁸ cm^?2. The nominal Al composition and in-plane strain ε _xx for the AlGaN layer grown on the GaN layer have been measured by asymmetric reciprocal-space mapping. Surface properties and cross-sectional views of the samples have been analyzed using atomic force microscopy (AFM) and field-emission scanning electron microscopy (FESEM), respectively. Room-temperature time-resolved photoluminescence and photoluminescence measurements have been performed on Al_0.18Ga_0.82N/Al_0.45Ga_0.55N double heterostructures and the GaN template. The interface recombination velocity (S) of AlGaN-based double heterostructures has been calculated using carrier decay time measurement, increasing from 8.7 × 10³ cm/s to 13.4 × 10³ cm/s with varying active layer thickness.     

Low temperature processed mosfet's using laser recrystallized polycrystalline silicon films

An n-channel MOS transistor was fabricated on a laser recrystallized polycrystalline silicon film at temperatures below 630°C. The gate oxide was sputter deposited at 200°C. Lasers were used for substrate recrystallization, implantation damage annealing and dopant drive-in. An electron field effect mobility higher than 100 cm²/V · sec. was observed on the finished transistors. With 10 V applied to the gate of the transistors for 2 hr, less than a 20 mV shift in threshold voltage was observed.     

Effects of oxygen on crystallization of amorphous silicon films and polysilicon TFT characteristics

Oxygen ions were implanted into the amorphous silicon film deposited at 540°C in order to study the effects of oxygen on the solid phase crystallization of silicon films. The resulting films were investigated using transmission electron microscopy, x-ray diffraction (XRD), and also by measuring the electrical characteristics of polycrystalline silicon thin film transistors (TFTs) fabricated in the crystallized films. The development of {111} texture as a function of annealing time is similar to films implanted with Si, with higher oxygen samples showing more texture. Transmission electron microscopy shows that the grain size of completely crystallized films varies little with oxygen concentration. The electrical performances of TFTs are found to degrade with increasing oxygen dose. The trap state density increases from 5.6 × 10¹²/cm² to 9.5 × 10¹²/cm² with increasing oxygen dose. It is concluded that for a high performance TFT, oxygen incorporation in the Si film should be kept to 10¹⁹/cm³ or less.     

Zinc Oxide Thin-Film Transistors Fabricated at Low Temperature by Chemical Spray Pyrolysis

We report the electrical behavior of undoped zinc oxide thin-film transistors (TFTs) fabricated by low-temperature chemical spray pyrolysis. An aerosol system utilizing aerodynamic focusing was used to deposit the ZnO. Polycrystalline films were subsequently formed by annealing at the relatively low temperature of 140°C. The saturation mobility of the TFTs was 2 cm²/Vs, which is the highest reported for undoped ZnO TFTs manufactured below 150°C. The devices also had an on/off ratio of 10⁴ and a threshold voltage of ?3.5 V. These values were found to depend reversibly on measurement conditions.