A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

一款用于LED驱动芯片的CMOS振荡器

研究一款适用于LED驱动芯片的CMOS振荡器电路.其工作原理是在环路振荡器中加入恒定电流源,以恒定电流对电容充电、MOS管对电容快速放电以产生锯齿波再经锁存器产生周期脉冲信号.与传统的环路振荡器相比,此电路的优点是振荡频率精确、波形稳定,振荡频率在一定的电源电压范围内对电源电压变化不敏感.此振荡器电路已经成功应用于一款LED驱动芯片中.     

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.     

Low-noise self-referenced CMOS oscillator

A new low-noise CMOS oscillator architecture is presented. The oscillator comprises of a loop formed by a switched capacitor integrator which sets the control voltage to a voltage controlled oscillator (VCO). The VCO output provides a clock for the integrator, thus closing the feedback loop. Phase noise reduction is obtained by suppressing the VCO noise by the feedback loop. Design considerations and simulation results supporting the architecture are presented.     

一种高精度高稳定性锯齿波振荡器的设计

设计了一种应用于DC/DC开关电源管理芯片的锯齿波振荡器,该电路利用内部基准电流源产生的电流对电容进行充放电,使得产生的锯齿波信号随电源电压和温度的变化较小,采用迟滞技术提高了锯齿波信号幅值.采用基于CSMC的0.5μmCMOS 工艺进行仿真.结果表明,该电路产生的振荡频率为5MHz,信号幅值为0-3V,电源电压在2....     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

Noise in CMOS Voltage Controlled Relaxation Oscillators

A low-noise voltage controlled relaxation oscillator (VCO) has been fabricated in a 2 micron CMOS process. The VCO uses a grounded external timing capacitor and a bypassed latch. A theoretical analysis is presented showing that the VCOs output phase noise is dominated by the undersampling of circuit noise arising principally from the comparators. A minor correction to equation (21) of Abidi and Meyer in [1] is also derived. The VCO design was modified to allow a comparison between two different comparator architectures whilst sharing a common VCO core of current sources, timing capacitor and latch. Spectrum analyzer measurements are presented which confirm the theoretical predictions and show that high frequency signals are aliassed down to appear as noise sidebands about the carrier frequency. The oscillator's phase noise was measured as –70 dBc/Hz at a 20 kHz offset when oscillating at 1.1 MHz.     

RF oscillator implementation using integrated CMOS surface acoustic wave resonators

This work is a proof of concept that a monolithic CMOS surface acoustic wave (SAW) resonator can function as an RF oscillator. The design of the oscillator includes the measurement characteristics of the CMOS SAW resonator, its matching networks, and RF amplifier is described. The integrated SAW resonator, with its operating frequency controlled by the spacing of its transducers was fabricated using a combination of CMOS plus post-CMOS processes. Based on the operation and performance of the SAW resonators, an equivalent circuit model of the CMOS SAW resonator was developed. A series resonant oscillator design was simulated using Microwave Office^TM. The designed matching network improves both the insertion losses and the phase slope of the resonator, while the RF amplifier provides sufficient gain to ensure oscillation. Measurements conducted on the RF-CMOS SAW oscillator demonstrated oscillation at 600 MHz.     

Design and implementation of a CMOS VCXO for FM stereo decoders

A circuit technique to simulate large variable capacitance of both positive and negative polarities over a given frequency range is discussed. The simulated capacitance can be varied by voltage control from -60 to +100 pF. The capacitor-simulating circuit is connected in parallel with a resonator to tune its parallel resonance. An oscillator with grounded resonator is also developed. Together with the variable capacitor, a voltage-controlled crystal oscillator (VCXO) is realized. The oscillation frequency of the oscillator can be tuned continuously from 452 to 461 kHz by voltage control. Detailed analyses to completely characterize the oscillator with a simple expression are presented. The prototype of the VCXO has been fabricated in a 4-μm standard CMOS process     

Realistic model of compact VLSI FitzHugh–Nagumo oscillators

In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.     

A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K _VCO) and the frequency step per a capacitor bank code (f _step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply.     

A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range

A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-/spl mu/m CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption.     

采用金属耦合电容实现级间匹配的射频功率放大器

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available,especially no high density capacitor.To address this problem,a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process.This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal（MIM） capacitor regarding their capacitor density.Detailed simulations are carried out for the leakage,the voltage dependency,the temperature dependency,and the quality factor between an inter-metal shuffled（IMS） capacitor and an MIM capacitor.Finally,an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application.The PA occupies 370 × 200 μm^2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.     

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a twostage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 X 200 μm2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.     

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.     

一种基于0.5μmCMOS工艺的补偿型电流控制振荡器设计

提出了一种基于比较器的CMOS电流控制振荡器电路,该振荡器采用偏置电流对电容充放电,产生精准锯齿波,比较器及后续电路产生时序方波作为比较器输入,从而产生周期振荡.自偏置电路利用电阻和PNP管相反的温度系数产生PTAT、NTAT两路电流,叠加得到一路与温度无关的基准电流、实现了温度补偿;高摆幅共源共栅电流镜结构具有高PSRR实现了电源电压补偿.本设计采用0.5 μmCMOS工艺,典型情况下,振荡器频率为1.224 MHz,占空比为50%,通过spectre仿真结果表明:该振荡器在3.3 V～5 V的工作电压下、-40～120℃温度范围内都具有较好的工作频率.     

一种用于斜坡补偿的振荡器设计

电流控制模式的开关电源变换器在占空比D>0.5时,存在次谐波振荡问题,因此必须进行斜坡补偿。在分析了峰值电流模式的DC/DC转换器中斜坡补偿原理的基础上,介绍了一种用于斜坡补偿的振荡电路,该振荡电路主要是通过对电容充放电的控制产生所需要的斜波,从而应用于DC/DC补偿。电路基于0.35μmCMOS工艺设计,并在Cadence下对电路进行整体仿真。结果表明该电路能在较大电源电压及温度范围内正常工作,能够提供1MHz的振荡信号。     

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 μA to 358 nA at 25 °C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process.