A rail-to-rail ping-pong op-amp

A rail-to-rail ping-pong op-amp achieves offset cancellation and 1/f noise reduction without folding of the input spectrum. The clocking scheme minimizes the clock feedthrough and the residual offset due to charge injection. With a clock frequency of 100 kHz, the residual offset is less than 100 μV, and the input referred noise is about 225 nV/Hz ^1/2. The rail-to-rail distortion at 1 kHz is lower than -71 dB. The total silicon area is 610×420 μm², and the circuit dissipates 1.5 mW from a single 5 V supply     

A switched-capacitor delta-sigma modulator with reduced sensitivityto op-amp gain

Low operational amplifier (op-amp) gain can degrade the performance of a switched-capacitor delta-sigma modulator (ΔΣM). A ΔΣM that incorporates a new gain-compensated switched-capacitor integrator is described. The resulting ΔΣM topology has reduced sensitivity to op-amp gain. Simulation and measurement results for an experimental ΔΣM that demonstrate the advantages of the new architecture are presented     

Measurements of 50 fs nonlinear gain time constant in semiconductorlasers

The symmetric and asymmetric nonlinear gain in 1.3-μm semiconductor lasers were measured in the frequency domain by a novel pump-probe technique using an external cavity traveling-wave semiconductor ring laser. A very short time constant of about 50 fs was measured as the dominant process. The data also indicated the presence of a smaller contribution approximately 15% of the magnitude of the dominant process and with a long time constant consistent with the effect of hot carriers     

Current-mode common-mode feedback for constant signal behaviour control in rail-to-rail input realisation

A new circuitry is introduced to maintain the constant signal behaviour for rail-to-rail input stages, and is suitable for general mixed-signal ultra-large-scale-integration and system-on-chip applications in contemporary nanoscale CMOS technologies. The constant signal performance is verified by experimental results in a 65 nm standard digital CMOS technology.     

General purpose rail-to-rail input circuit with constant behaviour for VLSI cell libraries

A general purpose rail-to-rail input stage suitable for analogue and mixed signal applications and compatible with modern submicron CMOS technologies, is introduced. The circuit provides, simultaneously, a constant small- and large-signal behaviour over the entire input common-mode voltage range, whilst imposing no appreciable constraint for high-frequency operation. Experimental results are given.     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

A true integrable noninverting integrator with adaptive gain constant

A circuit with a true noninverting integrator with an adaptive gain constant is described. The circuit uses a junction field effect transistor (JFET) as a voltage controlled resistor. This resistor is controlled to change the RC product of the circuit to achieve adaptivity. The adaptivity was observed over a frequency range of 1:3. The circuit is suitable for IC implementation because the performance characteristics are determined by a feedback loop, thereby making them independent of the usual tolerance in passive parameter values.     

A rotor time constant evaluation for vector-controlled inductionmotor drives

The online identification method for the rotor time constant of an induction machine is derived from the steady-state analysis of the machine space vectors. The indirect field orientation system is simulated to verify the convergence of the method in quasi-steady-state operation, independent of the initial controller parameters     

A real time infrared scene simulator

A real time simulator for infrared scenes is required to evaluate the performances of recognition and tracking of information processing machine in seeker. A real time simulator for infrared scenes composed of two Intel i860 processors is described in the paper. We first describe the hardware architecture of our system, then we give out schematic diagram illustrating how to compute the image sequences of infrared scenes based on our hardware system. Finally, experimental results indicate that the simulator can meet the needs of application in practice.     

A compact rail-to-rail output stage for CMOS operational amplifiers

This paper presents a CMOS output stage devised for driving heavy resistive loads. An operational amplifier of this type has been fabricated in a 3 μm double-polysilicon CMOS technology. With a supply voltage of ∓5 V and load of 470 Ω, the amplifier has a ∓4.6-V output swing and features a 60 mA short-circuit output current. Although simple, the proposed configuration enables the output transistors to be driven efficiently     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

Adequate SC model of op-amp with finite DC gain and bandwidth suitable for two-op-amp SC biquad analysis

An adequate model of a nonideal op-amp operating in a two-op-amp SC biquad is derived. The model leads to an equivalent SC circuit containing ideal components. Substitution of any op-amp in an SC biquad by its equivalent SC circuit allows the exact frequency response of the biquad to be found easily, taking into account the finite DC gain and bandwidth of op-amps.     

傅里叶变换全息信息存储的实时方法

我们设计的实验光路如图1所示。S为白光光源,被记录资料为O(x0,y0)。LCLV是混合场效应液晶光阀,透镜L_1将物之像I(x,y)成于光阀光导层OdS膜上,当满足液晶层电压〉液晶阈值电压时,就能使光导层与液晶上形成与写入光图像相对应的电压像。激光LA在BS_1上分束,一束作参考光,一束经K扩束后经L_2会聚并经P_1起偏,在BS_2上反射再经L_3成平行光照射LCLV并被返回,返回光受到液晶上电压像的调制,再经P_2检偏后得到与写入图像相对应的相干光图像O'(x',y')。O'(x',y')就是傅里叶变换光路中的物像。调节加在LCLV上的电压和频率,可得到O'(x',y')与O'(x,y)成线性关系:O'(x',y')=αO(x,y)。L_3是傅里叶变换透镜,P为其谱面处,谱面分布为     

基于DSP技术的光尾流实时探测方案

利用尾流的光散射特性对其进行探测 ,光散射谱强度分布的半值宽度随尾流中气泡群的密度而变化。基于成熟的信号处理技术 ,文中提出了对尾流进行实时探测的解决方案。系统采用CCD光采样 ,ADC数据采集及FIFO缓存 ,DSP数据处理三级流水线方式工作。充分发挥DSP处理器片内存储器容量大的特点 ,使用其片内数据缓冲区交替对CCD进行信号采集和数据处理 ;在进行数据处理过程中 ,处理器以中断方式读取FIFO缓存结果。     

A defect-tolerant systolic array implementation for real time image processing

An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved.The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester.The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders.High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.     

A TQR-iteration based adaptive SVD for real time angle andfrequency tracking

The transposed VR (TQR) iteration is a square root version of the symmetric QR iteration. The TQR algorithm converges directly to the singular value decomposition (SVD) of a matrix and was originally derived to provide a means to identify and reduce the effects of outliers for robust SVD computation. The paper extends the TQR algorithm to incorporate complex data and weighted norms, formulates a TQR-iteration based adaptive SVD algorithm, develops a real time systolic architecture, and analyzes performance. The applications of high resolution angle and frequency tracking are developed and the updating scheme is so tailored. A deflation mechanism reduces both the computational complexity of the algorithm and the hardware complexity of the systolic architecture, making the method ideal for real time applications. Simulation results demonstrate the performance of the method and compare it to existing SVD tracking schemes. The results show that the method is exceptional in terms of performance to cost ratio and systolic implementation     

利用实时时钟IC RV5C338A实现用软件校正时间

概述 我们知道,实时时钟IC一般把它产生的时间信号传递给微处理器等一类器件,作为它们的时钟信号。通常,由频率为32.768kHz晶振产生时钟信号,将该时钟信号进行1/2~(15)分频后形成秒信号,由时钟计数器对秒信号进行计数。 既然是处理时间信号,它的精度就成为人们十分关心的事情。晶体振荡器具有很高的频率精度,与RC振荡器和陶瓷振荡器相比,其精度要高两个数量级以上。另外同一型号产品之间的离散性也比较小,在常温下只有±20ppm的偏     

A VLSI architecture for the real time computation of discrete trigonometric transforms

The Discrete Trigonometric Transforms are defined as a class of transforms. An algorithm for calculating the Discrete Fourier Transform is extended to cover all members of the defined class. A VLSI architecture which provides for real time calculation of these transforms is presented. This architecture provides simple interconnections, identical processing elements and minimal control complexity.