可逆三值逻辑细胞阵列研究

本文提出一种新的三值平面逻辑细胞阵列，对这种阵列的性质进行了研究，这种阵列具有设计简单、可逆和易于推广等特点，不仅可用于逻辑函数的设计，还可实现具有较高安全性的数据加密与解密系统。     

归纳逻辑程序设计方法综述

归纳逻辑程序设计是机器学习与逻辑程序设计交叉所形成的一个研究领域,克服了传统机器学习方法的两个主要限制:即知识表示的限制和背景知识利用的限制,成为机器学习的前沿研究课题.首先从归纳逻辑程序设计的产生背景、定义、应用领域及问题背景介绍了归纳逻辑程序设计系统的概貌,对归纳逻辑程序设计方法的研究现状进行了总结和分析,最后探讨了该领域的进一步的研究方向.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

单片机在逻辑无环流可逆调速系统中的应用

在逻辑无环流可逆调速系统中，用8051单片机实现数字PI双闭环控制器，数字触发器及逻辑控制器的设计。     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

具有低量子代价的快速可逆逻辑综合方法研究

可逆逻辑是最子计算、低功耗设计和纳米技术领域的关键技术。目前可逆逻辑电路的综合方法效率较低、未能达到区域优化,所以,这些方法仪通用于小璎电路的综合。该文提出了一种基于Davio分解式的综合方法,该方法将逻辑函数转换成对应的正Davio决策图,然后通过对每个图节点模版匹配,最终生成可逆逻辑电路。此方法综合速度快,便于优化,适用于大型电路的综合。     

Easily Testable Cellular Carry Lookahead Adders

Cellular Carry Lookahead (CLA) adders are systematically implemented in arithmetic units due to their regular, well-balanced structure. In terms of testability and with respect to the classical Cell Fault Model (CFM), cellular CLA adders have poor testability by construction. Design-for-testability (DFT) modifications for cellular CLA adders have been proposed in the literature providing complete CFM testability making the adders either level-testable or C-testable. These designs impose significant area and performance overheads. In this paper, we propose DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance. Complete CFM testability is achieved without adding any extra inputs to the adder, with very small area and performance overheads, thus providing a practical solution. The proposed DFT scheme requires only 1 extra output and it is not necessary to put the circuit in a special test mode, while the earlier schemes require the addition of 2 extra inputs to set the circuit in test mode. A rigorous proof of the linear-testability of the adder is given and a sufficient linear-sized test set is provided that guarantees 100% CFM fault coverage. Surprisingly, the size of the proposed linear-sized test set is, in most practical cases, comparable or even smaller than a logarithmic-sized test set proposed in the literature.     

循环移位可编程序逻辑阵列的可测试性设计

本文研究了一种“芯片内部自测式”可编程序逻辑阵列(Built-in Sclf Tcst PLA)的设计方法:循环移位PLA(简称CS-PLA)法.CS-PLA与其他PLA可测试性设计方法相比,具有故障覆盖率高、对电路速度影响小、测试生成简单等特点,当PLA嵌入在芯片内部时,不需要单独的测试状态。其芯片面积成本随PLA的规模增大而降低,因此CS-PLA特别适用于大规模“嵌入式”PLA.     

An Efficient Method to Synthesize Reversible Logic by Using Positive Davio Decision Diagrams

Reversible logic is a key technique for quantum computing leading to quantum communication and quantum computer. However, the bottleneck of low efficiency in the synthesis procedure limits applications of reversible logic and cannot obtain optimized reversible circuits. In this paper, an efficient method based on positive Davio expansion to synthesize reversible circuits is proposed, which generates a positive Davio decision diagram for a logic function and transfers diagram nodes to reversible circuits. A matching template is given to help nodes transformation. The experimental results prove that compared with other synthesis methods, the proposed method can obviously optimize quantum cost and keep very short execution time.     

可测标准中抽象测试套件(ATS)的构造方法

阐述了一致性测试的概念、方法、形式和实施过程,在此基础上对可测标准与被测标准作了划分和理解,结合国际地理信息标准一致性与测试中所给出的构造抽象测试套件的框架,并以"自然资源和地理空间基础信息库(信息库)"项目中一些可测标准的ATS典型实例为研究对象,从中总结了抽象测试套件的构造规律和方法.该方法对可测标准的一致性条款中构造一组层级清晰、目标明确、高质高效的抽象测试套件具有重要的意义.     

Testable Designs of Multiple Precharged Domino Circuits

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults     

Forecasting Winning Bid Prices in an Online Auction Market - Data Mining Approaches

To solve information asymmetry problem on online auction, this study suggests and validates a forecasting model of winning bid prices. Especially, it explores the usability of data mining approaches, such as neural network and Bayesian network in building a forecasting model. This research empirically shows that, in forecasting winning bid prices on online auction, data mining techniques have shown better performance than traditional statistical analysis, such as logistic regression and multivariate regression.     

Testable design of large random access memories

In this paper we propose a method for testable design of large Random Access Memories. The design technique relies on modification of address decoders to achieve multi-writes and multi-reads during test mode. Almost no modification is required in the design of memory array.A number of different designs for decoders are proposed. In all the designs the objective has been to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM. Use of extra control and observation points is allowed as long as such points cause only a very small increase in the number of extra pins.We also propose the design of decorders in which only a limited number of cells of RAM are written to or read from during test mode.     

Design of Novel Testable and Diagnosable Phase-Frequency Detector

This paper presents a novel fully testable and diagnosable structure for phase-frequency detectors. All procedures of converting the conventional PFD to the fully testable one are reported step by step. Also, the probability-based testability of proposed architecture is calculated. In addition, area considerations related to new fully testable PFD are introduced completely. At last, the proposed structure is designed in both system level and circuit level. The results of fully testable PFD in 0.13-μm CMOS technology are shown. Simulation results confirm the theoretical analysis.     

Efficiency Enhancement of Permanent-Magnet Synchronous Motor Drives by Online Loss Minimization Approaches

In this paper, a new loss minimization control algorithm for inverter-fed permanent-magnet synchronous motors (PMSMs), which allows for the reduction of the power losses of the electric drive without penalty on its dynamic performance, is analyzed, experimentally realized, and validated. In particular, after a brief recounting of two loss minimization control strategies, namely, the “search control” and the “loss-model control,” both a new modified dynamic model of the PMSM (which takes into account the iron losses) and an innovative “loss-model” control strategy are presented. Experimental tests on a specific PMSM drive employing the proposed loss minimization algorithm have been performed, aiming to validate the actual implementation. The main results of these tests confirm that the dynamic performance of the drive is maintained, and in small motors enhancement up to 3.5% of the efficiency can be reached in comparison with the PMSM drive equipped with a more traditional control strategy.     

The Design and Implementation of an On-Line Testable UART

This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the most complex designs realised to date using on-line test approaches. The approach used—IFIS incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional redesign of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected.     

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.