基于常规逻辑门和原理图方式的可逆逻辑描述

针对可逆逻辑综合在设计较大规模可逆逻辑电路(ALU)时遇到的瓶颈问题。文中借用现行EDA技术的逻辑描述和验证能力,可逆逻辑门的功能表达式为依据,设计具有等功能的常规逻辑组合电路,通过等功能代换的方法,设计实现以常规原理图方式描述的可逆ALU。仿真图中显示的16种运算结果表明,该方法具有一定的可行性和有效性。     

可逆逻辑电路逻辑图及波形图图示化方法

针对以逻辑表达式给定的可逆逻辑电路进行分析,并绘制出其可逆逻辑电路图,仿真出波形图,并将由仿真结果得到的真值表进行可逆化构造。利用C语言编程实现,将相关结果以更直观的形式展现,这在可逆逻辑电路的研究中具有创新性。     

可逆三值逻辑细胞阵列研究

本文提出一种新的三值平面逻辑细胞阵列，对这种阵列的性质进行了研究，这种阵列具有设计简单、可逆和易于推广等特点，不仅可用于逻辑函数的设计，还可实现具有较高安全性的数据加密与解密系统。     

可逆逻辑表达式的识别和图示方法

可逆逻辑电路是仅包含可逆运算的新型电路,还可根除源于信息损失的能耗和发热,是研究与实现超低功耗集成电路、量子计算机及信息安全等的关键基础。文中针对可逆逻辑电路研究的需要,研究了通过识别可逆逻辑表达式提取可逆逻辑电路结构信息,并加以图形化显示的有效方法和可行算法,以便更形象、直观地表达可逆逻辑电路综合、优化的结果,进而为分析、理解和优化可逆逻辑电路提供方便。     

归纳逻辑程序设计方法综述

归纳逻辑程序设计是机器学习与逻辑程序设计交叉所形成的一个研究领域,克服了传统机器学习方法的两个主要限制:即知识表示的限制和背景知识利用的限制,成为机器学习的前沿研究课题.首先从归纳逻辑程序设计的产生背景、定义、应用领域及问题背景介绍了归纳逻辑程序设计系统的概貌,对归纳逻辑程序设计方法的研究现状进行了总结和分析,最后探讨了该领域的进一步的研究方向.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

基于量子可逆逻辑的桶型位移器设计

桶型位移器是高速处理器的常用部件,可在单周期内对数据字实现指定位数的位移操作,在量子可逆逻辑电路的基础上,本文提出了有n个输入位和k个控制位的位移器,记为（n,k）位移器。为综合可逆的位移器,提出了基于置换群分解的新方法,仅使用（3,1）位移器与控制交换门,快速生成较小量子代价的任意控制位移器,将k=[log(n)] 个相应的（n,1）位移器级联,生成可任意位移的（n,k）桶型位移器。     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

四量子可逆逻辑电路快速综合算法

量子可逆逻辑电路综合是以较小量子代价自动构造所求量子可逆逻辑电路.本文提出了一种新颖高效的4量子电路综合算法,巧妙构造置换的最短编码,通过对量子电路进行特定拓扑变换,无损压缩n量子最优电路占用内存空间近2×n!倍,通过对已生成最优电路的双向级联,可使用多种量子门,采用最小长度标准,以极高效率生成较长的4量子电路,如率先生成基于控制非门、非门、Toffoli门库的全部前8层共3120218828个电路,还可快速综合任意长度不超过16的最优电路,并对4量子标准测试电路进行快速且全面的优化.     

基于Q-M算法的量子可逆逻辑电路综合方法

提出了合并(化简)规则,并按合并规则修改了Q-M算法源码,获得积之异或和表达式,成功地实现了将不可逆操作转换为可逆操作。该规则应用于常规逻辑综合的Q-M算法移植到可逆逻辑综合中,以便利用可逆逻辑门来构造可逆逻辑电路。     

基于二分法量子可逆逻辑电路综合

 为了能以较小的代价自动高效地构造量子可逆逻辑电路,提出了一种新颖的量子可逆逻辑电路综合方法.该方法通过线拓扑变换和对换演算,利用递归思想,将n量子电路综合问题转换成单量子电路综合问题,从而完成电路综合,经过局部优化生成最终电路.该算法综合出全部的3变量可逆函数,未优化时平均需6.41个EGT门,优化后平均只需5.22个EGT门;理论分析表明,综合n量子电路最多只需要n2^n－1个EGT门.与同类算法相比,综合电路所用可逆门的数量大幅减少.同时该算法还避免了时空复杂度太大的问题,便于经典计算机实现.     

基于最小混乱度的三值可逆逻辑综合算法

 三值可逆逻辑综合是可逆逻辑综合的延伸和扩展.为了简化可逆网络,提高三值可逆逻辑门的通用性,对现有三值可逆控制门控制位的生效值扩展为0、1和2.在此基础上提出了基于最小混乱度原则的三值可逆逻辑综合算法.该算法根据三值可逆函数计算其对应真值表中每个变量的相对混乱度和绝对混乱度,以最小混乱度原则选取三值可逆逻辑门,直至真值表中的每个变量的混乱度为零,得到三值可逆网络.该算法的时间复杂度为O(n²×3ⁿ),空间复杂度为O(n×3ⁿ).实验结果表明,与现有已知算法对比,平均门数更少.     

单片机在逻辑无环流可逆调速系统中的应用

在逻辑无环流可逆调速系统中，用8051单片机实现数字PI双闭环控制器，数字触发器及逻辑控制器的设计。     

Social and Heuristic Approaches to Credibility Evaluation Online

The tremendous amount of information available online has resulted in considerable research on information and source credibility. The vast majority of scholars, however, assume that individuals work in isolation to form credibility opinions and that people must assess information credibility in an effortful and time‐consuming manner. Focus group data from 109 participants were used to examine these assumptions. Results show that most users rely on others to make credibility assessments, often through the use of group‐based tools. Results also indicate that rather than systematically processing information, participants routinely invoked cognitive heuristics to evaluate the credibility of information and sources online. These findings are leveraged to suggest a number of avenues for further credibility theorizing, research, and practice.     

基于变换的可逆逻辑电路量子代价优化方法

电路优化是可逆逻辑综合的关键问题。为解决可逆逻辑电路优化算法的复杂度高和可伸缩性差的问题,文中针对常见的以Toffoli为构件的可逆逻辑电路,分析归纳了其中相邻逻辑门的关系,提出了该类电路中子序列的移动和化简规则,进而给出了基于这些规则的可逆逻辑电路优化算法。并在此基础上,提出了利用模板匹配法对已被规则优化的电路进行深度优化的有效方法。通过Benchmark的电路测试,结果表明,该方法能够部分减少可逆电路的门数和控制位数,降低了构建可逆电路的代价。     

可逆逻辑门进化设计方法的CUDA实现

可逆逻辑门优化程度将直接影响可逆逻辑电路的整体优化,目前已有的优化方法难以实现全局最优。文中基于NCV门库,对遗传算法编码方案和适应度进行了改进,并将进化设计方法改造为CUDA架构下的并行算法应用到可逆逻辑门的优化。其不仅发挥了电路进化设计的全局优化能力,且在不增加硬件规模的前提下,明显提高了电路的搜索速度。     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

Online Fuzzy Logic Base Algorithm for Electricity Price Prediction

This paper presents a web-based system to predict the electricity prices. The proposed system captures the geographical location, weather forecast, and oil price for one week ahead. The captured parameters are fed to a fuzzy-logic-based algorithm to calculate electric energy prices. Based on predicted electricity prices, consumers can turn ON/OFF or reschedule operations of their home appliances to reduce their electricity bill. The proposed algorithm was developed and hosted in a utility server (U-server). On the consumer side, a home gateway (H-gateway), and a monitoring and control system was designed, built, and tested by using a single chip microcontroller.