Cr掩模在硅湿法刻蚀中的应用研究

针对硅湿法刻蚀中常见的SiO2、Si3N4掩模的缺点,提出了以Cr薄膜层为刻蚀掩模的新方法,并进行了相应的试验.试验结果表明,Cr掩模湿法刻蚀技术可用于硅半导体器件的制作.此项工艺为硅湿法刻蚀加工提供了一条新的技术途径.     

PCR生物芯片微反应腔的制作及其热分析

在PCR生物芯片的制作过程中,微反应腔制作是关键部分之一.本文利用硅基微机械加工工艺,分别采用湿法化学腐蚀、干法等离子体刻蚀及两者相结合的方法进行了微反应腔的制作.通过扫描电镜分析,证明干法和湿法腐蚀相结合的制作工艺能加工出较理想的微反应腔体.本文还利用ANSYS软件对微反应腔进行温度分布和热特性分析.     

PCR生物芯片微反应腔的制作及其热分析

在PCR生物芯片的制作过程中 ,微反应腔制作是关键部分之一。本文利用硅基微机械加工工艺 ,分别采用湿法化学腐蚀、干法等离子体刻蚀及两者相结合的方法进行了微反应腔的制作。通过扫描电镜分析 ,证明干法和湿法腐蚀相结合的制作工艺能加工出较理想的微反应腔体。本文还利用ANSYS软件对微反应腔进行温度分布和热特性分析。     

单晶硅各向异性湿法刻蚀的研究进展

单晶硅各向异性湿法刻蚀是制作硅基微电子机械系统(MEMS)器件的重要步骤之一,由于具有刻蚀均匀性好、批量大、成本低的优点而深受关注。首先回顾了单晶硅各向异性湿法刻蚀的刻蚀机理,比较了三种常用各向异性刻蚀液的刻蚀性质,讨论了刻蚀形状的控制技术。然后着重介绍了表面活性剂修饰的单晶硅各向异性湿法刻蚀速率和刻蚀表面光滑度等特性,以及面向MEMS应用的基于该刻蚀技术的各种微纳新结构;分析了表面活性剂分子在刻蚀过程中的作用,强调了表面活性剂分子在单晶硅表面的吸附性对改变刻蚀表面的物理性质的重要性。最后在此基础上,归纳了单晶硅各向异性湿法刻蚀的发展情况,探讨了其未来的发展方向。     

硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分 ,通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究 ,得到了合适的工艺条件以及较理想的硅尖     

硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分,通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究,得到了合适的工艺条件以及较理想的硅尖.     

PCR生物芯片微反应腔的制作及其热分析

在PCR生物芯片的制作过程中，微反应腔制作是关键部分之一。本文利用硅基微机械加工工艺，分别采用湿法化学腐蚀、干法等离子体刻蚀及两者相结合的方法进行了微反应腔的制作。通过扫描电镜分析，证明干法和湿法腐蚀相结合的制作工艺能加工出较理想的微反应腔体。本文还利用ANSYS软件对微反应腔进行温度分布和热特性分析。     

基于微细加工技术的微谐振腔型滤波器

设计了一种新工艺———利用硅微结构直接作为模具来制作微小固体染料激光器谐振腔型滤波器。首先通过组合刻蚀工艺制作硅模具 ,再利用硅模具复制得到微谐振腔。组合刻蚀工艺是采用深层反应离子刻蚀 (deep RIE)再结合EPW湿法刻蚀 (一种各向异性刻蚀技术 )。由于EPW湿法刻蚀对〈110〉面刻蚀速率较慢 ,可制作出具有光学镜面的侧壁〈110〉的硅模具 ,利用此模具可复制出正方形固态染料微谐振腔。以激光染料若丹明 6G掺杂的聚甲基丙烯酸甲脂 (PMMA)为工作物质 ,在调QNd∶YAG自倍频激光 5 32nm抽运下 ,得到 6 0 0nm波长的激光输出。这种谐振腔可应用在染料激光器和滤波器中 ,对其原理、设计、制作工艺和性能都作了介绍。     

掺杂GaN的湿法刻蚀研究

对掺杂GaN的湿法刻蚀研究进行了总结,回顾了不同的湿法刻蚀技术,包括传统的酸碱化学刻蚀和电化学刻蚀。从掺杂GaN的生长过程、表面化学组分和光电性质出发,深入地分析了湿法刻蚀的特性,对比了不同刻蚀方法的原理和效果。考虑到p-GaN的表面氧化层比较厚,接触电阻较大,能带向下弯曲不能进行光增强湿法刻蚀,重点阐述了p-GaN的传统湿法刻蚀和n-GaN的紫外光增强湿法刻蚀技术。与传统化学刻蚀相比,光增强湿法刻蚀具有更为广阔的前景。结合GaN基半导体器件的制作,对湿法刻蚀的主要应用进行了较为详细的归纳。目前,湿法刻蚀和干法刻蚀可以有效结合。将来湿法刻蚀有希望代替干法刻蚀。     

硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分，通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究，得到了合适的工艺条件以及较理想的硅尖。     

Mechanism for convex corner undercutting of (110) silicon in KOH

The cantilever is fabricated on (110) silicon wafer by anisotropic wet etching method in KOH; the sidewall of cantilever is {111} plane, and it is vertical to the substrate. The convex corner is undercut, and the concave corner structure corresponds with the design. The mechanism of the convex corner undercutting is explained by the theory of covalent bond density.     

硅各向异性腐蚀中生成直角补偿结构的新方法

Detailed characteristics of three classical rectangular convex corner compensation structures on（100） silicon substrates have been investigated, and their common design steps are summarized.By combining the basic method of a silicon wet anisotropic etching process, a general method of generating compensation structures for a rectangular convex corner is put forward.This calls for the following two steps：define the topological field and fit some borderlines together into practical compensation patterns.The rules, which must be obeyed during this process, are summarized.By introducing this method, some novel compensation patterns for rectangular convex corner structures are created on both（100） and（110） substrates, and finally simulation results are given to prove this new method＇s validity and applicability.     

基于MATLAB的硅各向异性腐蚀过程模拟

根据硅各向异性腐蚀特点,在硅各向异性腐蚀速率图基础上,提出算法,利用数学软件MATLAB模拟了几种简单掩膜图形的腐蚀过程.程序从二维掩膜描述出发,找到相关晶面,产生动态的三维几何结构的输出.并推导出凸角补偿时补偿条的相关尺寸.其结果对MEMS加工有一定参考价值.     

Analysis and prevention of convex corner undercutting in bulk micromachined silicon microstructures

Convex corner undercutting in <100> silicon is an undesired phenomena during bulk micromachining of crystalline silicon substrate using anisotropic wet chemical etching process. The present investigation concentrates on the studies of convex corner undercutting at the free end of silicon cantilever beams released by anisotropic etching process. It also reports a simple, space efficient compensation design for complete prevention of corner deformation. Various compensation patterns such as square, rectangle and superposition of square and rectangular blocks of various dimensions have been employed at the free end corners of cantilever beam to protect corner deformation due to undercutting. The experiment was carried out in 44 wt.% KOH at 70 °C using <100> oriented silicon wafer. Both n-type and p-type silicon wafers were used to study the variations in the nature of corner deformation. A simple empirical relation has been obtained from the experimental data to calculate the lateral dimensions of the compensation layout from the total etch depth required to release the structure.     

A novel method for etching trenches in silicon carbide

In this paper, a novel trench etching technique for silicon carbide is described. In this technique, ion implantation is used to first create an amorphous silicon carbide region. The amorphous layer is then etched away by wet chemical etching. Trenches of 0.3 to 0.8 μ have been obtained using a single implantaion/etching step. It has been demonstrated that deeper trenches can be obtained by repeating the implantation/etching step with platinum as a masking material. The etched surface was found to be smooth when compared with reactive ion etched surfaces reported for silicon carbide.     

Integrated bulk/SOI APD sensor: bulk substrate inspection with Geiger-mode avalanche photodiodes

A rapid assessment of bulk silicon quality after removal of the silicon-on-insulator (SOI) and buried oxide layer using both plasma and wet etch is compared with standard p-epi silicon by comparing the performance of avalanche photodiodes (APD) operated in Geiger-mode. Plasma etching of the buried oxide shows lower dark counts than wet etched or standard p-epi substrates.     

High-barrier Schottky diodes on p-type silicon due to dry-etching damage

It is known that the barrier height of Schottky diodes made to dry-etched silicon surfaces deviate from the barrier height values obtained for diodes fabricated on wet chemically etched or cleaved silicon. This effect, in cases where neither a substantial residue layer nor a surface film is formed, can be exploited to yield diodes on p-type Si that display barrier enhancement together with excellent diode ideality factors. It is shown that the barrier heights produced on p-type Si, by exploiting this effect of dry etching, can achieve a value of ∼0.75 eV which is ∼0.15 eV better than the best value reported for wet chemically etched or cleaved p-Si. When this barrier height value is attained, it is found to be independent of metallization. The same barrier height is achieved by two very different dry etching techniques: Ar⁺ion-beam etching (IBE) and CCl4reactive ion etching (RIE).     

背照式CMOS图像传感器的硅减薄湿法刻蚀工艺

针对背照式CMOS图像传感器制作工艺,提出了一种采用氢氧化四甲基铵液进行湿法刻蚀的背部硅片减薄工艺。分析了硅减薄工艺的整体流程,针对化学机械研磨后的湿法刻蚀工艺进行了实验。通过调整反应时间、硅片转速、喷嘴速度和摆幅,得到最优刻蚀参数,使厚度均值达到目标值,平整度控制在一定范围内。该湿法刻蚀工艺中,首先对硅片表面形貌进行修正,接着对硅片进行整体刻蚀,达到目标厚度,最后通过减薄得到BSI背部硅片。采用该硅片制作的图像传感器的成像质量得到提高。     

Thermal instability of Schottky diode barrier heights modified by inert ion sputter-etching damage

The barrier height of Schottky diodes made to dry-etched silicon surfaces differs from those fabricated on wet chemically etched silicon. Some have suggested utilization of this phenomenon to yield diodes for VLSI applications that display barrier enhancement to p-type silicon and barrier reduction to n-type silicon together with good diode ideality factors; however, it is shown here that the modified barrier heights can be dramatically unstable even when exposed to relatively low-temperature cycling, thus rendering this technique of enhancing the barrier height to p-type silicon and reducing the barrier height to n-type silicon inappropriate for conventional VLSI fabrication. It is hypothesized that the barrier instability is due to a localized silicide reaction or surface reconstruction occurring at the metal/silicon interface.