An untrimmed D/A converter with 14-bit resolution

Describes a monolithic 14-bit DAC which uses a new compensation technique for the DAC linearity, the `self-compensation technique', originated through a new concept. Since this technique automatically compensates for linearity error in the DAC by referring to a ramp function with about 17-bit linearity, a high precision DAC can be produced in monolithic form without the trimming of analog components. An experimental 14-bit DAC chip has been fabricated using analog compatible IIL technology and two-level metalization. A linearity error of less that /spl plusmn/1/2 LSB and a settling time of 1-2 /spl mu/s has been achieved.     

A sixteen-bit monolithic bipolar DAC

Describes a fully monolithic 16-bit digital-analog converter (DAC) which is fabricated with dielectric isolation and thin film nichrome resistors. The design uses a straightforward extension of techniques successfully used in lower resolution DACs. To achieve the greater accuracy needed for a 16-bit DAC, special layout techniques are used. An auxiliary R-2R ladder is introduced to provide a ground current cancellation scheme. The experimental results show that 16-bit resolution is possible with a typical settling time of 1 /spl mu/s. Improved performance over a temperature range of 0/spl deg/C-75/spl deg/C is observed with units exhibiting one-half an LSB differential and integral linearity of 14-bit resolution. The initial 16-bit accuracy approaches that of expensive hybrid modules, while the accuracy over wide temperature ranges surpasses anything presently reported.     

An 8-bit 100-MHz CMOS linear interpolation DAC

An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.     

A monolithic 8-bit D/A converter with a new scheme for error compensation

Discusses a modification of a monolithic bipolar 8-bit D/A converter (DAC) circuit based on the R-2R ladder method. It does not require transistor emitter size scaling. Voltages proportional to absolute temperature are introduced between the bases of the current generator transistors to compensate for the differences in their emitter-base voltages and thus maintain precision in the current division of the R-2R ladder. The compensation obtained by this method is adequate for 9- and 10-bit monolithic DAC's operating in a temperature range from -40/spl deg/C to 125/spl deg/C.     

A 500-MHz 8-bit D/A converter

An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/'s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher.     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

一种1.5 V 8位100 MS/s电流舵D/A转换器

基于新型的低压与温度成正比(PTAT)基准源和PMOS衬底驱动低压运算放大器技术,采用分段温度计译码结构设计了一种1.5V8位100MS/s电流舵D/A转换器,工艺为TSMC0.25μm2P5MCMOS。当采样频率为100MHz,输出频率为20MHz时,SFDR为69.5dB,D/A转换器的微分非线性误差(DNL)和积分非线性误差(INL)的典型值分别为0.32LSB和0.52LSB。整个D/A转换器的版图面积为0.75mm×0.85mm,非常适合SOC的嵌入式应用。     

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A Heterogeneous 16-Bit DAC Using a Replica Compensation

A highly monotonic very low power 16-bit 2-MS/s digital-to-analog converter (DAC) for high-resolution control loop systems is proposed and demonstrated. Replica compensation is used in improving the monotonicity of a heterogeneous DAC composed of a coarse current steering DAC and a fine resistor-ladder DAC. A complete DAC, including an on-chip bandgap reference and an output buffer, consumes only 0.6 mA with a 2.7-V supply. The 2.19-mm $^{2}$ DAC with 10-I/O bonding pads implemented in 0.18- $mu$m Bi-CMOS process achieves ${pm} 0.8$ least significant bit (LSB) differential nonlinearity, ${pm} 4$ LSB integral nonlinearity, and ${pm} $ 3-mV offset error at 2-MS/s sample rate.      

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC

A low voltage-power, 13-bit and 16 MSPS analog-to-digital converter (ADC) was implemented in 0.25-/spl mu/m one-poly five-metal standard CMOS process with MIM capacitors. This ADC used a constant-gm switch to improve the nonlinear effect and a telescopic operational transconductance amplifier with a wide-swing biasing technique for power saving and low supply voltage operation. The converter achieved a peak SNDR of 59.2 dB with 16.384 MSPS, a low supply voltage of 1.3V, and Nyquist input frequency of 8.75 MHz. The static INL of /spl plusmn/2.0 LSB and DNL of /spl plusmn/0.5 LSB were obtained. The total power consumption of this converter was 78 mW. This chip occupied 3.4 mm /spl times/ 3.6 mm area.     

A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

An 8-bit 2-ns monolithic DAC

An 8-bit resolution ultrahigh-speed monolithic digital-to-analog converter (DAC) is fabricated using super self-aligned process technology. In order to improve dynamic accuracy, which is determined by settling speed, clock feedthrough noise, and glitch, a number of circuit technologies are developed including a rise- and fall-time control switch driver, a low-noise flip-flop, and a differential buffer configuration. In addition, a chip assembly technology using a multilayer ceramic substrate is developed. The DAC exhibits a settling time to 8-bit accuracy of about 2 ns, a maximum conversion rate of 1 GHz, a glitch energy of 2 ps-V, and a 10-bit linearity error accuracy without trimming     

A novel noise efficient feedback DAC within a switched capacitor /spl Sigma//spl Delta/ ADC

Efficient sampling of the reference noise within a bilinear switched capacitor /spl Sigma//spl Delta/ analog-to-digital converter (ADC), resulting in improved thermal noise performance is presented. Bilinear integrators contain a zero at the Nyquist frequency, with the result that no charge is transferred from the reference when a transition occurs in the modulator output. The average noise power added by the reference digital-to-analog converter (DAC) can be reduced substantially if the reference DAC is sampled only when charge is to be transferred. For midscale inputs, the sampled noise from a single bit reference DAC is reduced by more than 5 dB. When multibit quantization and feedback is used the reference noise can be further suppressed, in the case of 5 bits of feedback the reference noise is reduced by more than 20 dB.     

一种采用厚膜混合工艺的10位高速D/A转换器

介绍了一种采用厚膜混合集成工艺制作的倒R-2R电阻网络结构的高速10位D/A转换器电路.重点分析了二极管电流开关对输出电流建立时间的影响,提出了一种改进型二极管电流开关结构,减少了二极管电流开关中电荷泄放引起的过冲,使电流建立时间大大减小,样品电路测试典型值为25 ns.     

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.     

基于非线性DAC的步进电机细分驱动IC的设计

文章详细论述了步进电机细分驱动的原理，设计了一款基于非线性DAC的细分驱动集成电路。重点讨论了3位非线性DAC的原理、权电阻网络的选择和计算，并给出了实际电路。HSPICE仿真证明了设计方案和理论分析的可行性和正确性。     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.