共查询到20条相似文献,搜索用时 15 毫秒
1.
电容器、电阻器和电感器等这类无源元件是电子线路中进行各项功能如信号去耦、开关噪声抑制、滤波和调谐的重要部件。电子工业持续小型化发展非常需要将这类无源元件集成到印制线路板(PCB)或多芯片组件里芯片下面的介质层上。在约8000亿块无源元件/年的市场里,目前只有不到3%是采用集成形式。 在各种无源元件中,电容器在节省实用面积方面需要特别关注,因为它用量相对较大,占用面积较多。除了节省实用面积之外,集成电容器具有寄生电容少、电 相似文献
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Effectiveness of multiple decoupling capacitors 总被引:5,自引:0,他引:5
The effectiveness of using the parallel combination of large-value and small-value capacitors to increase the frequency coverage of either one and overcome the effect of lead inductance is examined. Computed and experimental results are given that show this scheme is not significantly effective. The improvement at high frequencies is at most 6 dB over the use of only the large-value capacitance 相似文献
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Polycrystalline paraelectric perovskite thin films in the Pb-La-Ti-O or PLT (28 mol.% La) system have been studied. Thin (0.5-μm) films were integrated onto 3-in Pt/Ti/SiO2/(100) Si wafers by the sol-gel processing technique. Low-field dielectric measurements yielded dielectric permittivity and loss tangent of 1400 and 0.015, respectively, while high-field Sawyer-Tower measurements (P -E ) showed linear behavior up to 40 kV/cm, which approached saturation at 200 kV/cm. Pulse charging transient and current-voltage measurements indicated a high charge storage density (15.8 μC/cm2) and low leakage current density (0.50 μA/cm2) under a field of 200 kV/cm. The charging time for a 1-μm2 PLT capacitor at 200 kV/cm was estimated to be 0.1 ns. The preliminary data demonstrate that paraelectric PLT thin films have excellent potential for use in ULSI DRAMs and as decoupling capacitors 相似文献
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Ruggedness, wide capacitance range, high volumetric efficiency, and relatively attractive cost have been the main reasons for the popularity of ceramic chip capacitors. Continuing improvements in most of these categories promise to keep the ceramic chip in its present position of prominence. This article considers multilayer, single-layer, and screened-on configurations. In addition, relationships between size, capacitance, and cost are covered for three common ceramic formulations (NPO, W5R, and Z5U). 相似文献
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《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1964,52(12):1465-1468
This paper presents the characteristics of Al2 O3 capacitors formed by the relatively new technique of gaseous plasma anodization. This process can be incorporated into a thin-film deposition process cycle thereby providing the advantage of minimizing contamination possibilities. The formation technique is briefly described and device properties are presented in detail. 相似文献
7.
Modeling and simulation of power electronic converters 总被引:3,自引:0,他引:3
Maksimovic D. Stankovic A.M. Thottuvelil V.J. Verghese G.C. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(6):898-912
This paper reviews some of the major approaches to modeling and simulation in power electronics, and provides references that can serve as a starting point for the extensive literature on the subject. The major focus of the paper is on averaged models of various kinds, but sampled-data models are also introduced. The importance of hierarchical modeling and simulation is emphasized 相似文献
8.
电容器是实现电源的宽范围电压和电流组合的最关键的无源元件之一。尽管每种电容器都能储存电能,但对于特定的应用来说,电介质技术在电容器的选择中起着重要的作用。电容器在电源中最重要的应用是在存储能量、浪涌电压保护、EMI抑制和控制电路等方面。我们可以通过图1了解到针对不同的应用领域,这些电介质技术彼此竞争或互为补充的关系。储能储能型电容器通过整流器收集电荷,并将存储的能量通过变换器引线传送至电源的输出端。电压额定值为40~450Vdc、电容值在220~150 000μF之间的铝电解电容器(如EPCOS公司的B43504或B43505)… 相似文献
9.
We describe the modeling of prototype capacitors embedded in multilayered printed circuit boards. We present the design of these devices. We also report measurement and characterization results. The emphasis is on the modeling of via hole connections to the embedded capacitor, not on the technology of buried capacitors. Several designs have been compared with respect to their electrical behavior. In particular, several via hole configurations have been studied, because they are the main cause of parasitic behavior. With these buried capacitors, we obtained a reduction of the parasitic inductance of 80% compared to an equivalent discrete capacitor. This work has been carried out under a European Brite-EuRAM funded project COMPRISE (BE 96-3371). The objective of this project was to develop new materials and manufacturing processes to embed passive components (R, L, and C) within printed wiring structures fabricated from laminate materials. This technology enables the manufacture of space efficient and radio frequency (RF) optimal performing types of modules or board assemblies particularly suited to the market domain of portable and handheld communication and information technology products 相似文献
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It is explained that to simulate circuits containing negative inductances and capacitances using general-purpose simulators like SPICE, the networks under consideration must be transformed into suitable SPICE-compatible circuits. Criteria that the portion of the network containing the negative elements should meet are given. The SPICE network realizing these elements, when L and C are independent of frequency and time, is shown. An example of a Brune network is given 相似文献
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为了达到抑制谐波污染的目的,采用了并联混合型有源滤波器的方法,并在Matlab/Simulink平台针对并联混合型有源滤波器的各个组成部分建立了仿真模型,并对该APF进行了详尽的动态仿真。通过频谱图分析数据结果,说明了谐波得到有效的补偿,获得了比较满意的仿真效果,为并联混合型有源滤波器应用于实际提供了设计依据。 相似文献
13.
Xiao-Hong Du Bing Sheu 《Circuits and Devices Magazine, IEEE》2002,18(6):10-16
The ferroelectric capacitor model is the foundation for accurate simulation of ferroelectric hysteresis loops and minor loops, transitions between the loops under arbitrary voltage patterns, transient responses of ferroelectric capacitors to short voltage pulses with widths in the nano-second range, and temperature behaviors of ferroelectric capacitors. The simulation speed is the same as that for a typical nonlinear capacitor. To the circuit designers, a ferroelectric capacitor is represented as a two-port device like a capacitor. The parameters are extracted easily and reliably by curve fitting the measured hysteresis loops. The model is applicable to fast circuit simulations for large ferroelectric memory designs. 相似文献
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Boliolo A. Benini L. de Micheli G. Ricco B. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1997,5(4):473-488
In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser 相似文献
15.
In recent years, there has been an explosion in demand for smaller and lighter, more efficient, and less expensive power electronic supplies and converters. There are a number of reasons for this recent necessity, ranging from the need for smaller and cheaper power converters for consumer electronics (such as laptop computers and cellular phones) to the need for highly reliable power electronics for such items as satellite and military craft power systems, which are required to be highly efficient, light in weight, smaller in volume, and low cost. This paper discusses the concept of Integrated Power Modules (IPMs), in which the electronic control circuitry and the high power electronics of the converter are integrated into a single compact standardized module. The advantages and disadvantages of such an approach will be discussed in reference to the current industry standard for power electronics design and packaging. The researchers will then take the readers through the IPM design, including basic circuit topology layout, module fabrication processes, and finally thermal considerations. 相似文献
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Electro-thermal characterization and simulation of integrated multi-trenched XtreMOSTM power devices
J. Rhayem B. Besbes R. Blečić S. Bychikhin G. Haberfehlner D. Pogany B. Desoete R. Gillon A. Wieers M. Tack 《Microelectronics Journal》2012,43(9):618-623
This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using multi-trenched XtreMOSTM devices. Electrical device data is collected by pulsed and DC measurements. Thermal data is collected through on-chip sensors and through a full surface high resolution transient interferometric mapping (TIM). For the first time a data driven segmented electro-thermal transient model is proposed to accurately describe the thermal profile behavior for the mutli-trenched devices. Further investigations of the thermal heating impact on the driver due to the low thermal conductivity of the trenches (SiO2) have been carried out. The results of the investigations have been discussed for two different gate to source (VGS) bias conditions: VGS below the temperature compensation point (TCP), which is a bias condition that might lead to a thermal runaway, and VGS above TCP. 相似文献
18.
Grounding of capacitors in integrated circuits 总被引:7,自引:0,他引:7
Fabrication techniques indicate that it is easier to obtain earthed capacitors than unearthed ones in integrated circuits. To take advantage of these techniques, a method to earth all capacitors, by replacing them with earthed gyrator-capacitor combinations, is described here. 相似文献
19.
《Electron Device Letters, IEEE》1982,3(5):127-129
The performance of a high-yield tantalum oxide capacitor for use in GaAs monolithic microwave integrated circuits is described. The integral metal-insulator-metal sandwich structure is reactively sputter-deposited at low temperatures, compatible with a photoresist lift-off process, on semi-insulating GaAs substrate. Dielectric constants of 20-25 were achieved in the capacitors fabricated. An initial application of this process as an interstage coupling capacitor for a two-stage preamplifier is given. 相似文献
20.
Popovich M. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(3):217-228
Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response. 相似文献