Recovery of shifted MOS parameters induced by focused ion beam exposure

The effects of focused ion beam (FIB) exposure on MOS transistors within a circuit were examined. It was found that FIB exposure does not cause parameter shifts as long as the gate is connected to the drain of other MOS transistors. However, the threshold voltage (V/sub t/) does shift during isolating the gate using a FIB. Further FIB exposure on MOS transistors with a floating gate is shown to cause larger shifts. Thermal annealing was studied to recover shifted V/sub t/. We demonstrated that a 400/spl deg/C-450/spl deg/C anneal could recover shifted V/sub t/ almost completely. Ninety percent recovery can be reached by annealing at 400/spl deg/C-450/spl deg/C for 1-2 hours, and V/sub t/ shifts can be reduced to about 10 mV.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Gate oxide breakdown on nMOSFET cutoff frequency and breakdown resistance

Gate oxide breakdown effect on CMOS RF devices has been examined. The breakdown spot resistance and total gate capacitance of nMOS transistors decrease with stress. The analytical equation of cutoff frequency including the gate oxide breakdown effect is derived. The impact of oxide breakdown on the performance of an LC oscillator is evaluated. The oscillation frequency of the LC oscillator increases with oxide breakdown.     

电抗器IGBT电路实现原理

通过引用零值器与泛值器的概念设计无铁磁材料电抗器,将绝缘栅双极晶体管(IG-BT)器件用零值器与泛值器等效表示,用零值器与泛值器设计频率固定的电压反向型和电流反向型电抗器。根据IGBT器件等效成零值器与泛值器总是连接在一起的特点,将零值器与泛值器设计的电压反向型和电流反向型电抗器进行等效变换,最后用IGBT器件变换零值器与泛值器,得到了IGBT电路实现频率固定的电压反向型和电流反向型电抗器原理电路。     

Towards the global modeling of InGaAs-based pseudomorphic HEMTs

We utilize a 3D full-band Cellular Monte Car- lo (CMC) device simulator to model ultrashort gate length pseudomorphic high-electron-mobility transistors (p-HEMTs). We present the static dc device characteristics and rf response for gate lengths ranging from 10 nm to 50 nm. Preliminary passive results using 3D full-wave Maxwell solver are also presented to illustrate the usefulness of and insight that a future coupled full-band/full-wave simulator will provide in more accurately, modeling the high frequency performance of p-HEMTs.     

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, \(\mathrm{I_{ON} , I_{OFF}, V_{T}}\), and the unity gain cut-off frequency \(\mathrm{(f_{T}}\)) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.     

The application of an ordered mesoporous silica film to a GaAs device

Pseudomorphic high electron mobility transistors (PHEMTs) are promising devices for use in millimeter-wave and optical communications systems due to their excellent high frequency and low-noise performances. In order to further improve the performance of these devices, their gate lengths must be reduced to the technological limit and a small gate resistance must be realized. However, shorter gates result in an increase of short channel effects that limit microwave performance. In order to reduce the gate resistance, T-shaped gates with large cross-sectional areas are required. However, the thickness and dielectric constant of the passivation layer have major impacts on the gate capacitance. In this study, an ordered mesoporous silica film was introduced as a passivation layer between T-gates. Si₃N₄ with a dielectric constant of 7.4 and ordered mesoporous silica with a dielectric constant of 2.48 were used as passivation layers. The Si₃N₄ dielectric layer and the ordered mesoporous silica film were stacked together and the device characteristics were investigated.     

Numerical simulation of small silicon partially insulated MOSFETs

The scaling of conventional MOS bulk transistors with gate lengths below 100 nm seems to be difficult due to short channel effects. Especially the adjustment of the threshold voltage V _th is difficult because of the rapid drop down at shorter gate lengths. For low power consumption and high speed applications SOI technologies have been developed, but floating body effects, increasing leakage currents, kink phenomena and decreased heat dissipation occur in SOI-FETs. To combine the benefits of conventional and SOI-MOSFETs and to avoid the disadvantages, partially insulated FETs (Pi-FETs) with oxide regions under source and drain are candidates for scaling down the gate length into the deep submicron area [1–3, 5, 6]. We present the results of several numerical simulations to compare conventional bulk transistors, SOI-FETs and Pi-FETs in their static and dynamic behaviour.     

Hot-carrier reliability comparison for pMOSFETs with ultrathinsilicon-nitride and silicon-oxide gate dielectrics

The degradation of 100-nm effective channel length pMOS transistors with 14 Å equivalent oxide thickness Jet Vapor Deposition (JVD) Si₃N₄ gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 Å Si₃N₄ transistors is compared to reliability of 16 Å SiO₂ transistors     

Analysis and modeling of LC oscillator reliability

In this paper, MOS device degradations due to hot carrier and gate oxide breakdown are shown experimentally, and their effects on the NMOS LC oscillator have been evaluated analytically and through SpectreRF simulation. The reduction in transconductance of the differential pair transistors may cause the oscillation to cease. The amplitude of oscillation reduces as the equivalent tank resistance decreases due to the breakdown effect on the MOS varactor. The reduction of amplitude reduces the tank capacitances, and therefore shifts the frequency of oscillation and increases the oscillator phase noise. The tank amplitude of the oscillator is derived analytically. A closed-form expression for the average capacitance of the varactor that accounts for large-signal effects is presented. Finally, a set of guidelines to design an LC oscillator in reliability is presented.     

A new F(ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs

In this paper, we present 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics^? software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). We then use this new algorithm to explore the effect of local constrictions on the performance of nanowire MultiGate Field-Effect Transistors (MuGFETs). We show that cross-section variations in a nanowire result in the formation of energy barriers that can be used to improve the on/off current ratio and switching characteristics of transistors: (1) A small constriction resulting in a barrier of the order of a 0.1 eV can be used as an effective means to improve the subthreshold slope and minimize the on/off current ratio degradation resulting from SD tunneling in ultra scaled transistor, and (2) We also report a new variable barrier transistor (VBT) device concept that is able to achieve sub-kT/q subthreshold slope without using impact ionization or band-to-band tunneling. Intra-band tunneling through constriction barriers is used instead. The device is, therefore, fully symmetrical and can operate at very low supply voltages. A subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the widest current range reported so far.     

Mechanism of Electron Trapping and Characteristics of Traps in HfO2 Gate Stacks

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.     

Differential pass transistor pulsed latch

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full swing of internal nodes. Also, the power consumption of the proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.13 um CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.     

Optimization of saddle junctionless FETs for extreme high integration

In this work, a saddle junctionless field effect transistors with optimal gate structure is proposed for extreme high integration. The forward and reverse I–V characteristics of the optimal saddle JL FETs have been extensively investigated by analyzing the influence of doping concentration, the height of the source/drain extension region and the gate structure engineering from physical insight. Design optimization has also been performed and the optimal parameters have been proposed.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

Implementation of current source inverter for power lineconditioning

A current source inverter (CSI) designed to operate as a power line conditioner (PLC) is presented. Only six power switches are required for the CSI. A 5 kVA test model of the CSI has been built using insulated gate bipolar transistors (IGBTs) controlled by a digital signal processor (DSP). To determine system performance, experimental results are compared with computer simulations of an innovative adaptive frequency domain control for pulse width modulated (PWM) switching of the CSI. The adaptive frequency domain control algorithm performs quite well in both steady-state and transient conditions. The steady-state distortion factor of the line current is reduced from 28% to 5% or less. The displacement power factor is corrected from 0.5 lagging to unity. Single cycle PLC response time to a step change in load is demonstrated     

乌东德水电站泄洪减振水弹性模型试验研究

本文基于水工模型试验,利用乌东德水弹性模型,研究了不同表孔开度对下游边坡和底部基岩振动的影响,同时利用BP神经网络建立了两种振动预测模型,将泄洪流量分为三个流量级,提出各流量级下的泄洪减振优化方案。结果表明:(1)表孔单独泄流时,当开度增大,基岩的振动基本上呈增大趋势,但当表孔全开时,基岩的振动反而呈减小趋势,边坡的振动则总是跟开度正相关。对于表孔中孔联合泄洪,底部基岩的振动往往在4m开度时最小,但边坡的振动情况比较复杂。(2)两种振动预测模型都有良好的精度,并且单独建立表孔中孔联合泄洪工况的预测模型可以提高精度。(3)流量很小时,单独采用多个表孔小开度泄洪;流量一般时,充分利用中孔泄洪,开启较少表孔且采用4 m开度;流量较大时,中孔全开,表孔采用多孔小开度泄洪。