MCM的工艺技术发展

一、引言多芯片模块MCM：（MultichipModule）的基本概念是：把多块裸露的IC芯片组装在同一块多层高密度互连基板上，并封装在同一管壳中，形成一个多芯片功能组件。MCM是一种先进的电子组装技术，与过去的混合IC概念的关键区别在于“多块”“裸露”芯片直接组装在多层高密度互连基板上，若把一些单片器件组装在PC板上，则不能叫做MCM。采用MCM技术，其芯片之间的节距可缩得极小，层与层间以通孔金属化导线互连，因此，其多层互连线比常规PC板或混合IC要缩短一个数量级，由此导致一系列引人注目的重大优点。国际上的研究开发结果…     

一种低成本的硅垂直互连技术

1引言 近年来，随着三维叠层封装技术和MEMS封装技术的发展，硅垂直互连技术正在受到越来越多的重视【1】。这一技术通过在硅片上制作出垂直电互连来实现芯片正面与背面或上下芯片之间的互连，从而缩短了互连线的长度并为芯片提供更为优异的电性能。其应用包括：台面MOS功率器件的倒装芯片封装【2】、垂直集成传感器阵列的制造【3】、RF-MEMS器件的封装【4】、高性能硅基板的开发【5】和芯片的三维叠层封装【6】。     

一种用于胎压传感器的新型系统级封装技术

TPMS IC是TPMS系统模块的关键核心器件,需要采用系统级封装(SiP)技术。对TPMS IC的一种新型SiP封装技术作了研究分析。在引线框架上引入电路板中介层,改善了芯片间电气互连与分布,增大了引入薄膜电阻电容元件的设计弹性。采用预成型模制部分芯片的封装技术,满足了IC与MEMS芯片不同的封装要求,还增强了SiP产品的可测试性和故障可分析性。采用敞口模封、灌装低应力弹性凝胶和传感器校准测试相结合的方法有效避免封装应力对MEMS压力传感器的影响。     

Cadence为IC封装推出解决方案

Cadence日前发布了SPB16．2版本,着力解决电流与芯片封装设计问题。这次的最新版本提供了高级IC封装系统级封装（SiP）小型化、设计周期缩减和DFM驱动设计,以及一个全新的电源完整性建模解决方案。这些新功能可以提高从事单芯片和多芯片封装／SiP的数字、模拟、RF和混合信号IC封装设计师的效率。新规则和约束导向型自动化能力的推出,解决了高密度互连（HDI）衬底制造的设计方法学问题,     

多端互连线网络布线时延的研究

互连线时延是集成电路设计中非常重要的影响因素。本文根据Elmore延迟模型推导出多端互连线的延迟估算公式，得出了在满足设计规则的前提下，多端互连线网络应尽量遵守的布线规则，即互连线之间不要有重叠，且从源点到每个终点都要走最短的曼哈顿路径。这种布线规则可以在不增加芯片面积的基础上使互连线时延减少，这对指导高速IC芯片的版图设计有重要的理论和实践指导意义。     

面阵列CSP仿真的可靠性预测

随着SMT技术的发展，集成电路封装互连，尤其是球栅阵列和面阵列CSO的互连可靠性成为人们关注的重点。其关系到这些互连技术的推广应用。本通过一系列的模拟实验，获取一些关键数据，从而开发出分析IC封装互连可靠性的新方法。并采用SRS软件作为预测可靠性的工具。创建和分析IC封装互连的新方法可为当今高性能产品提供可靠的需求。具有球栅阵列(BGA)特征的较新型的元件封装与面阵列互连组合形成了一类应用技术，这种技术能够容纳更多引线数，占用的板子空间小，而且还实现了宽间隙下的互连。对面阵列引线性能的调研已成为人们密切关注的领域，并对此展开了一系列的研究。必须考虑为下一代封装开发可靠的、低应力互连的方法。由于BGA不同于传统的组装方法，不存在将柔性引线弯曲连接的工艺步骤，显然，迫切期望为面阵列封装开发依附引线。因此，而为新BGA在开发一类小型化的IC封装以满足这种迫切需求。我们将其统称为芯片级封装(CSP)。已开发出这些小型化封装可使许多与倒装芯片技术相关的性能优势尽可能地满足广大用户的要求，而不需要用户来处理和组装未被保护的裸芯片。为获得引线柔性或释放应力，需要采用一种综合策略。首先，有必要说明可能会影响现代焊接的组件的合理应用的许多设计特性。     

三维封装中引线键合技术的实现与可靠性

结合半导体封装的发展,研究了低线弧、叠层键合、引线上芯片、外悬芯片、长距离键合和双面键合6种引线互连封装技术;分析了各种引线键合的技术特点和可靠性.传统的引线键合技术通过不断地改进,成为三维高密度封装中的通用互连技术,新技术的出现随之会产生一些新的可靠性问题;同时,对相应的失效分析技术也提出了更高的要求.多种互连引线键合技术的综合应用,满足了半导体封装的发展需求;可靠性是技术应用后的首要技术问题.     

有机封装基板的芯片埋置技术研究进展

有机封装基板为IC提供支持、保护和电互联,是IC封装最关键的材料之一。系统级、微型化和低成本是IC封装的趋势,将有源、无源元件埋入封装基板,可以充分利用基板内部空间,释放更多表面空间,是减小系统封装体积的重要途径,因此有机封装基板的芯片埋置技术发展迅速。主要介绍有机封装基板的埋置技术发展过程,归纳了有机基板芯片埋置工艺路线类型,着重介绍了近十年不同的芯片埋置技术方案及其应用领域。在此基础上,对有机封装基板的埋置技术研究前景进行了展望。     

3-D叠层芯片封装技术

超大规模集成电路(VLSI)技术的不断革新要求 IC 产品和其它系统元素之间的互连数目不断增长,而且互连线要短,电信号线仍将维持大容量和高速度。为了跟上 IC 对封装的速度和密度增长的要求,需要更多地使用薄膜多芯片组件。这里推荐一种既能满足将来的要求又能突破先前已有方法的局限性的3-D 叠层技术。     

数模混合高速集成电路封装基板协同设计与验证

介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法.合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标.封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输.封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径.     

An overview of electrical characterization techniques and theory for IC packages and interconnects

This paper reviews current approaches to the electrical characterization and modeling of IC packages and interconnects. An overview of both frequency and time-domain measurement methods and summaries of equivalent circuit model selection and extraction methodologies are included. Additionally, an overview of numerical methods for electromagnetic modeling is included for completeness. Finally, relevant case studies from the literature are summarized to further supplement the discussed techniques. The focus is primarily on high-frequency signal related characterization and power integrity issues are not directly considered in this paper. This paper is presented in the context of the growing requirement for package and interconnection electrical models for high-speed and miniaturized systems.     

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.     

IC封装中键合线传输结构的仿真分析

随着高频高速集成电路制造工艺的不断进步,电子封装技术的发展也登上了一个新高度。作为微电子器件制造过程中的重要步骤之一,封装中的传输线、过孔、键合线等互连结构都可能对电路的性能产生影响,因此先进的集成电路封装设计必须要进行信号完整性分析。介绍了一种键合线互连传输结构,采用全波分析软件对模型进行仿真,着重分析与总结了键合线材料、跨距、拱高以及微带线长度、宽度五种关键设计参数对封装系统中信号完整性的影响,仿真结果对封装设计具有实际的指导作用。     

基于QFP技术的高频集成电路封装设计

通过对标准QFP引线框架的改造,实现了一种高频集成电路芯片的封装设计。介绍了利用电磁场仿真软件进行封装的3D建模,并提取封装结构的模型参数,进行信号完整性分析的方法。实例验证表明,此方法以较低的封装成本,较好地减少了长键合线及框架引脚对高频信号的影响,在现有的封装技术基础上提供了实现高频/高速集成电路封装的新思路。     

印制电路板设计与工艺对信号完整性的影响

信号完整性问题是高速数字系统的研究重点,其主要形式有反射、串扰与电磁干扰等。影响信号完整性的物理互连层包括集成电路、芯片封装、印制电路板和系统级连接四个部分,芯片和印制电路板是当前信号完整性研究的主要对象。本文主要阐述了印制电路板设计和工艺对信号完整性的影响。     

Aluminium-based packaging platform for led using selectively anodising method

An aluminium-based packaging platform with microreflector and electrical via for an interconnection electrode is first proposed for a package component of a light-emitting diode (LED). The electrode-guided interconnection with 180 mum thickness has been successfully fabricated by using the selectively anodising process, and not by either the plating or the solder paste technique. The reflector was formed during the isotropic etching process. By mainly a two-step chemical process, the LED packaging platform integrated microreflector and electrical via in one body was developed in a low-cost process.     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

RFID标签引脚阻抗的建模与计算

射频识别(RFID)标签的封装中,芯片与天线靠各向异性导电胶(ACA)连接。ACA的性质导致了芯片的引脚与天线连接处会有较大的阻抗,影响了标签的电参数,会对标签读写距离产生不利的影响。分析了芯片引脚处阻抗对标签的电性能的影响,对该处电阻与寄生电容进行了建模和计算。最后,依据理论计算了一款天线的引脚阻抗,并据此对该天线进行了优化与测试,验证了理论的正确性。